Datasheet

ManualsBrandsBROADCOM ManualsOptoelectronics & DisplaysHigh-speed Digital-CMOS-Logic-Gate Optocoupler DIP 8 Type (misc.) 50 MBd, CMOS, 2 ns

Description

Available in either 8-pin DIP or SO-8 package style respec-

tively, the HCPL-7723 or HCPL-0723 optocoupler utilize

the latest CMOS IC technology to achieve outstanding

speed performance of minimum 50 MBd data rate and

2 ns maximum pulse width distortion.

Basic building blocks of HCPL-7723/0723 are a CMOS

LED driver IC, a high speed LED and a CMOS detector

IC. A CMOS logic input signal controls the LED driver

IC, which supplies current to the LED. The detector

IC incorporates an integrated photodiode, a high speed

transimpedance amplier, and a voltage comparator with

an output driver.

Functional Diagram

SHIELD

**V

DD1

NC*

GND

DD2

GND

, INPUT LED1

OFF

TRUTH TABLE

(POSITIVE LOGIC)

NC*

LED1

, OUTPUT

* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT

UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.

PIN 7 IS NOT CONNECTED INTERNALLY.

** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN

PINS 1 AND 4, AND 5 AND 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of

this component to prevent damage and/or degradation, which may be induced by ESD.

Features

• +5 V CMOS compatibility

• High speed: 50 MBd min.

• 2 ns max. pulse width distortion

• 22 ns max. prop. delay

• 16 ns max. prop. delay skew

• 10 kV/µs min. common mode rejection

• –40 to 85°C temperature range

• Safety and regulatory approvals:

UL recognized

– 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for

option 020

– 3750 Vrms for 1 min. per UL1577 for HCPL-0723

CSA component acceptance notice #5

IEC/EN/DIN EN 60747-5-2

– Viorm = 630 Vpeak for HCPL-7723 option 060

– Viorm = 560 Vpeak for HCPL-0723 option 060

Applications

• Digital eldbus isolation: CC-Link, DeviceNet, Probus,

SDS, Isolated A/D or D/A conversion

• Multiplexed data transmission

• High speed digital input/output

• Computer peripheral interface

• Microprocessor system interface

HCPL-7723/0723

50 MBd 2 ns PWD High Speed CMOS Optocoupler

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Summary of content (12 pages)

PAGE 1
HCPL-7723/0723 50 MBd 2 ns PWD High Speed CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Available in either 8-pin DIP or SO‑8 package style respectively, the HCPL-7723 or HCPL-0723 optocoupler utilize the latest CMOS IC technology to achieve outstanding speed performance of minimum 50 MBd data rate and 2 ns maximum pulse width distortion.
PAGE 2
Package Outline Drawings HCPL-7723 8-Pin DIP Package 9.65 ± 0.25 (0.380 ± 0.010) TYPE NUMBER 8 7 6 7.62 ± 0.25 (0.300 ± 0.010) 5 OPTION 060 CODE* 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE A XXXXV YYWW 1 1.19 (0.047) MAX. 2 3 4 1.78 (0.070) MAX. 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.
PAGE 3
HCPL-7723 Package with Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 6 7 8 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 3 2 10.9 (0.430) 4 2.0 (0.080) 1.27 (0.050) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.635 ± 0.130 2.54 (0.025 ± 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES).
PAGE 4
Device Selection Guide 8-Pin DIP (300 mil) Small Outline SO-8 HCPL-7723 HCPL-0723 Ordering Information HCPL-0723 and HCPL-7723 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
PAGE 5
Solder Reflow Temperature Profile Regulatory Information The HCPL-7723/0723 have been approved by the following organizations: 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. 200 PEAK TEMP. 245°C PEAK TEMP. 240°C 2.5°C ± 0.5°C/SEC. UL Recognized under UL1577, component recognition program, File E55361. SOLDERING TIME 200°C 30 SEC. 160°C 150°C 140°C PEAK TEMP. 230°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC.
PAGE 6
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards.
PAGE 7
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 125 °C Ambient Operating Temperature[1] TA –40 85 °C Supply Voltages VDD1, VDD2 0 6.0 Volts Input Voltage VI –0.5 VDD1 +0.5 Volts Output Voltage VO –0.5 VDD2 +0.5 Volts Average Output Current IO 10 mA Lead Solder Temperature 260°C for 10 sec., 1.
PAGE 8
Switching Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V. Parameter Symbol Propagation Delay Time to Logic Low Output[3] Typ. Max.
PAGE 9
Package Characteristics All Typical Specifications are at TA = 25°C. Parameter Input-Output Momentary Withstand Voltage[7,8,9] Symbol –7723 VISO Option 020 –0723 Min. Typ. Max. Units Test Conditions 3750 V rms RH ≤ 50%, t = 1 min, 5000 TA = 25°C 3750 Input-Output Resistance[7] R I-O 10 12 Ω VI-O = 500 V dc Input-Output Capacitance C I-O 0.6 pF f = 1 MHz Input Capacitance[10] C I 3.
PAGE 10
Application Information Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Bypassing and PC Board Layout The HCPL-7723/0723 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-7723/0723 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.
PAGE 11
Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern.
PAGE 12
For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.