Specifications

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™

Revision: April 3, 2013

1300 Henley Court | Pullman, WA 99163

(509) 334 6306 Voice and Fax

Doc: 502-182 page 1 of 22

Overview

The Nexys3 is a complete, ready-to-use

digital circuit development platform based on

the Xilinx Spartan-6 LX16 FPGA. The

Spartan-6 is optimized for high performance

logic, and offers more than 50% higher

capacity, higher performance, and more

resources as compared to the Nexys2’s

Spartan-3 500E FPGA. Spartan-6 LX16

features include:

 2,278 slices each containing four 6-

input LUTs and eight flip-flops

 576Kbits of fast block RAM

 two clock tiles (four DCMs & two PLLs)

 32 DSP slices

 500MHz+ clock speeds

In addition to the Spartan-6 FPGA, the

Nexys3 offers an improved collection of

peripherals including 32Mbytes of Micron’s

latest Phase Change nonvolatile memory, a

10/100 Ethernet PHY, 16Mbytes of Cellular

RAM, a USB-UART port, a USB host port for

mice and keyboards, and an improved high-

speed expansion connector. The large FPGA

and broad set of peripherals make the

Nexys3 board an ideal host for a wide range

of digital systems, including embedded

processor designs based on Xilinx’s

MicroBlaze.

Nexys3 is compatible with all Xilinx CAD

tools, including ChipScope, EDK, and the

free WebPack. The Nexys3 uses Digilent's

newest Adept USB2 system that offers FPGA

and ROM programming, automated board

tests, virtual I/O, and simplified user-data

transfer facilities.

A comprehensive collection of board support IP and reference designs, and a large collection of add-

on boards are available on the Digilent website. Please see the Nexys3 page at www.digilentinc.com

for more information.

Cellular RAM

16MByte

High-Speed

Expansion

USB HID Host

Mouse/Keyboard

Spartan-6

XC6SLX16

CSG324C

Basic I/O

LEDs, Btns, Swts

Pmod Port

Expansion

USB-UART

Clock 100MHz

Adept USB2

Config & data

SPI PCM (x4)

Nonvolatile

Memory

16MByte

10/100

Ethernet PHY

Parallel PCM

Nonvolatile

Memory

16MByte

8-bit VGA

 Xilinx Spartan-6 LX16 FPGA in a 324-pin BGA package

 16Mbyte Cellular RAM (x16)

 16Mbytes SPI (quad mode) PCM non-volatile memory

 16Mbytes parallel PCM non-volatile memory

 10/100 Ethernet PHY

 On-board USB2 port for programming & data xfer

 USB-UART and USB-HID port (for mouse/keyboard)

 8-bit VGA port

 100MHz CMOS oscillator

 72 I/O’s routed to expansion connectors

 GPIO includes 8 LEDs, 5 buttons,8 slide switches and

4-digit seven-segment display

 USB2 programming cable included

Summary of content (22 pages)

PAGE 1
Nexys3™ Board Reference Manual Revision: April 3, 2013 1300 Henley Court | Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Nexys3 is a complete, ready-to-use digital circuit development platform based on the Xilinx Spartan-6 LX16 FPGA. The Spartan-6 is optimized for high performance logic, and offers more than 50% higher capacity, higher performance, and more resources as compared to the Nexys2’s Spartan-3 500E FPGA.
PAGE 2
Nexys3 Reference Manual Configuration After power-on, the Spartan-6 FPGA board must be configured (or programmed) before it can perform any functions.
PAGE 3
Nexys3 Reference Manual JTAG (both jumpers loaded), and board power is cycled. The FPGA will automatically reject any .bit files that are not built for the proper FPGA. After being successfully programmed, the FPGA will cause the "Done" LED to illuminate. Pressing the Reset button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from one of the PCM devices if the J8 Mode jumper is set to BPI or SPI mode.
PAGE 4
Nexys3 Reference Manual Adept System Digilent's Adept high-speed USB2 system can be used to program the FPGA and PCM devices, run automated board tests, add PC-based virtual I/O devices (like buttons, switches, and LEDs) to FPGA designs, and exchange register-based and file-based data with the FPGA. Adept automatically recognizes the Nexys3 board and presents a graphical interface with tabs for each of these applications.
PAGE 5
Nexys3 Reference Manual The configuration tool supports programming from any valid ROM file produced by the Xilinx tools. After programming, board power can either be cycled or the Reset button can be pressed to program the FPGA from the PCM device selected by the J8 mode jumper. If programming with a .bit file, the startup clock must be set to CCLK. All three memory devices (the PCM's and the cellular RAM) can be fully tested by clicking the Full Test button.
PAGE 6
Nexys3 Reference Manual Register I/O The register I/O tab requires that a corresponding IP block, available in the Parallel Interface reference design (DpimRef.vhd) on the Adept page of the Digilent website, is included and active in the FPGA. This IP block provides an EPP-style interface, where an 8-bit address selects a register, and data read and write buttons transfer data to and from the selected address.
PAGE 7
Nexys3 Reference Manual I/O Expand The I/O Expand tab works with an IP block in the FPGA to provide additional simple I/O beyond the physical devices found on the Nexys3 board. Virtual I/O devices include a 24LED light bar, 16 slide switches, 16 push buttons, 8 discrete LEDs, a 32-bit register that can be sent to the FPGA, and a 32-bit register that can be read from the FPGA. The IP block, available in the Adept I/O Expansion reference design (AdeptIOExpansion.
PAGE 8
Nexys3 Reference Manual Nexys3 Power Supplies Supply 3.3V 2.5V 1.2V 1.8V Circuits FPGA I/O, USB ports, Clocks, ROM & RAM I/O, Ethernet Optional voltage for Bank0 and VHDC connector FPGA Core RAM and ROM core Power Select Jumper JP1 Device IC13: LTC3633 IC14: LTC3619 IC13: LTC3633 IC14: LTC3619 Amps (max/typ) 3A / 200mA 800mA / 0mA 3A / 0.2 to 1.0A 400mA / 0.1 to 0.3A JP4 VUEXP USB port Micro-USB VU EN EN Power Jack 3A 1.2V 3A 3.
PAGE 9
Nexys3 Reference Manual controller (similar to any SRAM controller). When operated in synchronous mode, continuous transfers of up to 80MHz are possible. The parallel PCM device (Micron part number NP8P128A13T1760E) is organized as 8Mwords of 16bits each. It contains 128 individually erasable 64K-blocks, one of which is subdivided into four 16K “parameter blocks” that can offer increased data protection.
PAGE 10
Nexys3 Reference Manual ADDR(25:0) DATA(15:0) Shared signals See Table L18 M16 R10 H18 V4 OE WE CLK ADV WAIT RAM only L15 K15 K16 M18 MT-CE MT-UB MT-LB MT-CRE Cellular RAM Parallel PCM only L17 T4 SPI PCM Spartan6 P30-CE P30-RST AE14 AF14 AF20 AG21 AG17 AH18 Parallel PCM CS# SDI/DQ0 SDO/DQ1 WP#/DQ2 HLD#/DQ3 SCK SPI PCM Nexys3 Memory Bus Signal Assignments ADDR25: ADDR24: ADDR23: ADDR22: ADDR21: ADDR20: ADDR19: ADDR18: ADDR17: Doc: 502-182 F15 F16 C17 C18 F14 G14 D17 D18 H12 Address Bus AD
PAGE 11
Nexys3 Reference Manual Ethernet PHY The Nexys3 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8710) paired with an RJ-45 Ethernet jack with integrated magnetics. EDK-based designs can access the PHY using either the xps_ethernetlite IP core or the xps_ll_temac IP core. The Nexys3 Base System Builder (BSB) support package automatically generates a test application for the Ethernet MAC; this can be used as a reference for creating custom designs.
PAGE 12
Nexys3 Reference Manual Spartan-6. Each tile includes two Digital Clock Managers (DCMs) and four Phase-Locked Loops (PLLs). DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32.
PAGE 13
Nexys3 Reference Manual incorrect bit files will automatically be rejected. Note the PIC24 reads the FPGA's mode, init, and done pins, and can drive the PROG pin as a part of the programming sequence. HID Controller To access the USB host controller, EDK designs can use the standard PS/2 core (non-EDK designs can use a simple state machine).
PAGE 14
Nexys3 Reference Manual FE FF Resend. FE directs keyboard to re-send most recent scan code. Reset. Resets the keyboard. The keyboard can send data to the host only when both the data and clock lines are high (or idle). Since the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal.
PAGE 15
Nexys3 Reference Manual Mouse status byte 1 0 L R 0 1 XS YS XY YY P Start bit Stop bit X direction byte 1 0 Y direction byte X0 X1 X2 X3 X4 X5 X6 X7 P 1 Stop bit Start bit 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P 1 Stop bit Idle state Start bit Idle state Mouse Data Format VGA Port The Nexys3 board uses 10 FPGA signals to create a VGA port with 8-bit color and the two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync).
PAGE 16
Nexys3 Reference Manual those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon Anode (entire screen) fall under the influence of the much larger Cathode ray tube electrostatic force that results from the entire phosphor-coated display surface of the CRT Deflection coils being charged to 20kV (or more).
PAGE 17
Nexys3 Reference Manual corresponds to the number of horizontal passes the cathode makes over the display area, and a number of “columns” that corresponds to an area on each row that is assigned to one “picture element” or pixel. Typical displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of rows and columns determines the size of each pixel.
PAGE 18
Nexys3 Reference Manual Basic I/O The Nexys3 board includes eight slide switches, five push buttons, eight individual LEDs, and a four digit seven-segment display. The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output).
PAGE 19
Nexys3 Reference Manual Seven-Segment Display The Nexys3 board contains a four-digit common anode seven-segment LED display. Each of the four digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark.
PAGE 20
Nexys3 Reference Manual asserted, then a “7” will be displayed in digit position 2. If AN0 and CB, CC are driven for 4ms, and then A1 and CA, CB, CC are driven for 4ms in an endless succession, the display will show “17” in the first two digits. An example timing diagram for a four-digit controller is provided. Expansion Connectors The Nexys3 board has a 68-pin VHDC connector for high-speed/parallel I/O, and an 8-pin Pmod connector for lower speed and lower pin-count I/O.
PAGE 21
Nexys3 Reference Manual VHDC Connector Pinout IO1-P: IO2-P: IO3-P: IO4-P: IO5-P: IO6-P: IO7-P: IO8-P: IO9-P: IO10-P: B2 D6 B3 B4 C5 B6 C7 D8 B9 D11 IO1-N: IO2-N: IO3-N: IO4-N: IO5-N: IO6-N: IO7-N: IO8-N: IO9-N: IO10-N: A2 C6 A3 A4 A5 A6 A7 C8 A9 C11 IO11-P: IO12-P: IO13-P: IO14-P: IO15-P: IO16-P: IO17-P: IO18-P: IO19-P: IO20-P: C10 G9 B11 B12 C13 B14 F13 C15 D14 B16 IO11-N: IO12-N: IO13-N: IO14-N: IO15-N: IO16-N: IO17-N: IO18-N: IO19-N: IO20-N: A10 F9 A11 A12 A13 A14 E13 A15 C14 A16 Pmod Connectors
PAGE 22
Nexys3 Reference Manual Built-In Self Test A demonstration configuration is loaded into the BPI PCM device on the Nexys3 board during manufacturing. This demo bit file is available for download from the Digilent website. If the demo configuration is present in the BPI PCM device and the Nexys3 board is powered on in BPI mode, a simple demo project will allow basic hardware verification.