Release Notes

5 Memory Errors and Dell PowerEdge YX4X Server Memory RAS Features
bits). This means that any one bit among the 72-bits accessed from DRAM can be incorrect and
PowerEdge server hardware will automatically correct it – regardless of cause.
Advanced ECC
Advanced ECC Feature Support Table
Platforms Supported
Intel Platforms: 
(Xeon SP Families Only)
AMD Platforms: 
(All EPYC Families)
DIMMs Supported
x4 DIMMs: 
(Use of x4 DIMMs May Provide DRAM Device Correction)
x8 DIMMs: 
(Use of x8 DIMMs May Provide Nibble Correction)
Advanced ECC is a RAS feature that provides error correction on single-bit and multi-bit failures that are
bound within 4-bits (nibble) of memory accesses. When used in conjunction with DIMMs based on x4
DRAM devices, Advanced ECC may provide error correction to an entire single DRAM device. This type of
error correction that covers an entire DRAM device has been branded in various forms, most
popularized as Chipkill and Single Device Data Correction (SDDC). Advanced ECC is a highly complex
feature that is based on the concept of Single Symbol Correcting – Double Symbol Detecting (SSC-DSD)
Reed-Solomon error correcting and detection code [3]. At a high level, SSC-DSD works by breaking up
cache line accesses into ‘code words’ which in turn are made up of multi-bit symbols. The size of these
symbols can vary depending upon the processor architecture. But regardless if the symbol size is 4-bits
or 32-bits, as the SSC-DSD name implies, the coding is designed such that a single symbol may be
corrected for various combinations of bit errors. In many cases, depending on the SSC-DSD
implementation, all bits in a symbol could be corrected if they had errors. Studies have indicated that
error correcting codes based on SSC-DSD may provide up to 42x better fault correction and avoidance
than SEC-DED ECC alone [4].
An example SSC-DSD coding implementation is represented in the following figures where a 64-byte
cache line is broken into eight code words (Figure 1). Each code word is made up of eighteen 8-bit
symbols and can be broken down into 128-bits of data and 16-bits of ECC (8-bits of CRC and 8-bits of
parity). The data and ECC is arranged (as shown by the various colors) such that all bits from an entire
symbol are located within a single x4 DRAM device. Depending on the SSC-DSD coding implementation,
Advanced ECC may correct various combinations of multiple bits error patterns within a single symbol
including the entire symbol itself (Figure 2). However, a pair of two single bit errors across two symbols
would yield an uncorrectable error (Figure 3).