Release Notes

7 Memory Errors and Dell PowerEdge YX4X Server Memory RAS Features
As described earlier, SSC-DSD implementations will vary based on CPU platform architecture and
generation. This results in different error correction coverage and memory configuration requirements
to enable Advanced ECC. The current SSC-DSD coding implementation in PowerEdge YX4X servers with
AMD EPYC 7xx1 processors will provide data correction on all error patterns within a single symbol. The
current SSC-DSD coding implementation in PowerEdge YX4X servers with Intel Xeon SP processors will
provide data correction on most of the possible error patterns within a single symbol. In PowerEdge
YX4X servers, Advanced ECC is now enabled by default as part of Independent Mode on all Intel Xeon SP
and AMD EPYC based platforms. PowerEdge YX4X servers with Intel Xeon E or lower tier processors do
not provide Advanced ECC capabilities.
It was earlier mentioned that Advanced ECC, when used in conjunction with x4 DIMMs, may provide
error correction to a single DRAM device including failure of the entire device itself. This is achieved by
the processor organizing memory accesses such that a given DRAM device is only contributing data to a
single symbol – and through SSC-DSD, any one symbol can be fully redundant. On the other hand,
DIMMs with x8 DRAM devices will straddle two symbols and may only provide partial device correction
at the nibble level. An uncorrectable error will occur should both symbols within a x8 DRAM device
experience an error or the entire device fail.
1
. . .
32 4
5 76 8 9 1110 12 13 1514 16 65 6766 68
X
X
X
X
73 7574 76
78 8079 81 82 8483 85 86 8887 89 137 139138 140
69 7170 72
141 143142 144
Figure 4 – Advanced ECC with x8 DIMMs allows a nibble per DRAM to be protected but not the entire device
Adaptive Double Device Data Correction (ADDDC)
ADDDC Feature Support Table
Platforms Supported
Intel Platforms: 
(Xeon SP Families Only)
AMD Platforms: 
DIMMs Supported
x4 DIMMs: 
x8 DIMMs: 
Memory Configuration
Required
• Two or more memory ranks per memory channel
Adaptive Double Device Data Correction (ADDDC) is an Intel platform-specific technology that allows for
two DRAM devices to sequentially fail before loss of fault-avoidance. ADDDC is only supported with x4
DIMM populations and requires a memory configuration of two or more memory ranks channel (two
DIMMs per channel or a single DIMM with multiple ranks).
ADDDC works by having the BIOS track the number of correctable errors per DRAM bank. If the number
approaches a threshold deemed unsafe by BIOS, then ADDDC is activated and the failing DRAM bank is
dynamically mapped out while a ‘buddy’ bank is mapped in to take its place. The DIMM continues to