Release Notes

9 Memory Errors and Dell PowerEdge YX4X Server Memory RAS Features
Memory Page Retire (MPR) is a feature implemented by PowerEdge server BIOS that instructs operating
systems to stop using memory page locations (4 KB in size) that BIOS has deemed as potentially
unhealthy – essentially removing it from the operating system’s memory pool. BIOS makes the
determination of a potentially unhealthy memory page based on a proprietary PowerEdge server
algorithm that takes into account correctable error patterns and error rates at a given memory page
location.
Studies into memory page retirement (aka off-lining) have found that MPR can reduce memory error
rates by as much as 94% [5]. This feature is automatically enabled in BIOS and will be activated provided
the operating system supports memory page retirement. Fortunately, most modern operating systems
support the capability of receiving such memory page retirement requests.
Memory Rank Sparing
Memory Rank Sparing Feature Support Table
Platforms Supported
Intel Platforms: 
(Xeon SP Families Only)
AMD Platforms: 
DIMMs Supported
x4 DIMMs: 
x8 DIMMs: 
Memory Configuration
Required
• Single Rank Sparing – Two or more memory ranks per memory
channel
• Multi Rank Sparing – Three or more memory ranks per memory
channel
Memory Rank Sparing is a memory RAS feature available on Intel platforms that will reserve one or
more memory ranks per channel as spares for failover. When the PowerEdge server memory health
monitor has determined that one of the ranks in a memory channel has degraded, it will trigger rank
sparing failover. The failover process consists of checking the health of the spare rank(s) through patrol
scrubbing then seamlessly copy the contents of the degraded rank to the spare rank(s). Memory rank
sparing is disabled by default and can be enabled in BIOS setup if required.