Reference Manual

16-Axis MACRO CPU Software Reference Manual
34 16-Axis MACRO Station MI-Variable Reference
Example:
To set a PWM frequency of 10 kHz:
MI900 = (117,964.8 kHz / [4*10 kHz]) - 1 = 2948
To set a PWM frequency of 7.5 kHz:
MI900 = (117,964.8 kHz / [4*7.5 kHz]) - 1 = 3931
MS{anynode},MI903 Hardware Clock Control Channels 1-4
Range: 0 - 4095
Units: MI903 = Encoder SCLK Divider
+ 8 * PFM_CLK Divider
+ 64 * DAC_CLK Divider
+ 512 * ADC_CLK Divider
where:
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ Encoder SCLK Divider)
PFM_CLK Frequency = 39.3216 MHz / (2 ^ PFM_CLK Divider)
DAC_CLK Frequency = 39.3216 MHz / (2 ^ DAC_CLK Divider)
ADC_CLK Frequency = 39.3216 MHz / (2 ^ ADC_CLK Divider)
Default: 2258 = 2 + (8 * 2) + (64 * 3) + (512 * 4)
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
PFM_CLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
DAC_CLK Frequency = 39.3216 MHz / (2 ^ 3) = 4.9152 MHz
ADC_CLK Frequency = 39.3216 MHz / (2 ^ 4) = 2.4576 MHz
MI903 controls the frequency of four hardware clock frequencies – SCLK, PFM_CLK, DAC_CLK, and
ADC_CLK – for channels 1-4 on a 16-Axis MACRO Station (on a 4-axis piggyback board with jumper
E1 connecting 1-2). It is a 12-bit variable consisting of four independent 3-bit controls, one for each of
the clocks. Each of these clock frequencies can be divided down from a starting 39.3216 MHz frequency
by powers of 2, 2
N
, from 1 to 128 times (N=0 to 7). This means that the possible frequency settings for
each of these clocks are:
Frequency Divide by Divider N in
1/2
N
39.3216 MHz 1 0
19.6608 MHz 2 1
9.8304 MHz 4 2
4.9152 MHz 8 3
2.4576 MHz 16 4
1.2288 MHz 32 5
611.44 kHz 64 6
305.72 kHz 128 7
Very few 16-Axis MACRO Station users will be required to change the setting of MI903 from the default
value.
The encoder sample clock signal SCLK controls how often the 16-Axis MACRO Station's digital
hardware looks at the encoder and flag inputs. The 16-Axis MACRO Station can take at most one count
per SCLK cycle, so the SCLK frequency is the absolute maximum encoder count frequency. SCLK also
controls the signal propagation through the digital delay filters for the encoders and flags; the lower the
SCLK frequency, the greater the noise pulse that can be filtered out. The SCLK frequency should
optimally be set to the lowest value that can accept encoder counts at the maximum possible rate.