Reference Manual

16-Axis MACRO CPU Software Reference Manual
16-Axis MACRO Station Memory and I/O Map 83
16-19 Sync packet slave node number control
20-23 Master number control
X:$C08E Not used
Y:$C08F MACRO Ring Status and Control
Bits: 0 Data overrun error (cleared when read)
1 Byte violation error (cleared when read)
2 Packet parity error (cleared when read)
3 Data underrun error (cleared when read)
4 Master station enable
5 Synchronizing master station enable
6 Sync packet received (cleared when read)
7 Sync packet phase lock enable
8 Node 8 master address check disable
9 Node 9 master address check disable
10 Node 10 master address check disable
11 Node 11 master address check disable
12 Node 12 master address check disable
13 Node 13 master address check disable
14 Node 14 master address check disable
15 Node 15 master address check disable
X:$C08F DSPGATE2 clock control register
Bits (Bits 0-11 comprise I993)
0-2: SCLK Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
3-5: PFM Clock Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
6-8: DAC Clock Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
9-11: ADC Clock Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
12: Phase Clock Direction (0=output, 1=input)
(This must be 1)
13: Servo Clock Direction (0=output, 1=input)
(This must be 1)
14-15: Not used (report as zero)
16-19: Phase Clock Frequency Control n (I997)
(f=MAXPHASE / [n+1], n=0-15)
20-23: Servo Clock Frequency Control n
(f=PHASE / [n+1], n=0-15)
DSPGATE2 Channel 1* and Channel 2*.
These are the Auxiliary channels that support the JHW Port
Chan # 1* 2*
Hex
[$C090] [$C098]
Y:$C09x Channel n Time between last two encoder counts (SCLK cycles)
X:$C09x Channel n Status Word
Bits: 0-2 Captured Hall Effect Device (UVW) State
3 Invalid demultiplex of C, U, V, and W
4-7 Not used (reports as 0)
8 Encoder Count Error (0 on counter reset, 1 on illegal transition)
9 Position Compare (EQUn) output value