User's Manual

Table Of Contents
16-Axis MACRO CPU User Manual
Turbo PMAC2 Software Setup for MACRO Station 21
The following table lists the conversion table entries to use these registers. Remember that the second
line of the entry should always be $018000:
Register First Line
Value
Register First Line
Value
Motor #1 Previous Phase Pos. $2800B2 Motor #17 Previous Phase Pos. $2808B2
Motor #2 Previous Phase Pos. $280132 Motor #18 Previous Phase Pos. $280932
Motor #3 Previous Phase Pos. $2801B2 Motor #19 Previous Phase Pos. $2809B2
Motor #4 Previous Phase Pos. $280232 Motor #20 Previous Phase Pos. $280A32
Motor #5 Previous Phase Pos. $2802B2 Motor #21 Previous Phase Pos. $280AB2
Motor #6 Previous Phase Pos. $280332 Motor #22 Previous Phase Pos. $280B32
Motor #7 Previous Phase Pos. $2803B2 Motor #23 Previous Phase Pos. $280BB2
Motor #8 Previous Phase Pos. $280432 Motor #24 Previous Phase Pos. $280C32
Motor #9 Previous Phase Pos. $2804B2 Motor #25 Previous Phase Pos. $280CB2
Motor #10 Previous Phase Pos. $280532 Motor #26 Previous Phase Pos. $280D32
Motor #11 Previous Phase Pos. $2805B2 Motor #27 Previous Phase Pos. $280DB2
Motor #12 Previous Phase Pos. $280632 Motor #28 Previous Phase Pos. $280E32
Motor #13 Previous Phase Pos. $2806B2 Motor #29 Previous Phase Pos. $280EB2
Motor #14 Previous Phase Pos. $280732 Motor #30 Previous Phase Pos. $280F32
Motor #15 Previous Phase Pos. $2807B2 Motor #31 Previous Phase Pos. $280FB2
Motor #16 Previous Phase Pos. $280832 Motor #32 Previous Phase Pos. $281032
Sometimes the conversion table will process data sent back to Turbo PMAC2 through I/O nodes, which
are mapped into Turbo PMAC2 as X-registers. Often this is done in cases of dual feedback or loop-
around-loop configurations. Because these I/O nodes use X-registers instead of Y-registers, they use the
$6 conversion method (X/Y data) instead of the $2 conversion method (Y data only) and specify a 24-bit
offset in the second line of the entry
The following table shows entries for processing the data in the 24-bit register 0 of the first six I/O nodes
for each MACRO IC:
Register First Line
Value
Register First Line
Value
MACRO IC 0 Node 2 Reg. 0 $6F8420 MACRO IC 2 Node 2 Reg. 0 $6FA420
MACRO IC 0 Node 3 Reg. 0 $6F8424 MACRO IC 2 Node 3 Reg. 0 $6FA424
MACRO IC 0 Node 6 Reg. 0 $6F8428 MACRO IC 2 Node 6 Reg. 0 $6FA428
MACRO IC 0 Node 7 Reg. 0 $6F842C MACRO IC 2 Node 7 Reg. 0 $6FA42C
MACRO IC 0 Node 10 Reg. 0 $6F8430 MACRO IC 2 Node 10 Reg. 0 $6FA430
MACRO IC 0 Node 11 Reg. 0 $6F8434 MACRO IC 2 Node 11 Reg. 0 $6FA434
MACRO IC 1 Node 2 Reg. 0 $6F9420 MACRO IC 3 Node 2 Reg. 0 $6FB420
MACRO IC 1 Node 3 Reg. 0 $6F9424 MACRO IC 3 Node 3 Reg. 0 $6FB424
MACRO IC 1 Node 6 Reg. 0 $6F9428 MACRO IC 3 Node 6 Reg. 0 $6FB428
MACRO IC 1 Node 7 Reg. 0 $6F942C MACRO IC 3 Node 7 Reg. 0 $6FB42C
MACRO IC 1 Node 10 Reg. 0 $6F9430 MACRO IC 3 Node 10 Reg. 0 $6FB430
MACRO IC 1 Node 11 Reg. 0 $6F9434 MACRO IC 3 Node 11 Reg. 0 $6FB434
The second line of one of these entries is $018018. The first 018 specifies a 24-bit width. The second
018 specifies a 24-bit offset from the Y-register’s bit 0, which puts the least significant bit used at the X-
register’s bit 0.