Reference Guide

PMAC Quick Reference Guide
10 Introduction
All enabled PLCC programs execute one scan (to the end or to an ENDWHILE statement) starting from lowest
numbered to highest uninterrupted by any other background task (although it can be interrupted by higher
priority tasks). At power-on\reset, PLCC programs run after the first PLC program runs.
The receipt of a control character from any port is a signal to PMAC that it must respond to a command. The
most common control character is the carriage return (<CR>), which tells PMAC to treat all the preceding
alphanumeric characters as a command line. Other control characters have their own meanings, independent of
any alphanumeric characters received. Here PMAC will take the appropriate action to the command, or if it is an
illegal command, it will report an error to the host.
Between each scan through each background PLC program, PMAC performs its housekeeping duties to keep
itself properly updated. The most important of these are the safety limit checks (following error, overtravel limit,
fault, watchdog, etc.) Although this happens at a low priority, a minimum frequency is ensured because the
watchdog timer will trip, shutting down the card, if this frequency gets too low.
Observations
PMAC has an on-board watchdog timer circuit whose job it is to detect a number of conditions that could
result in dangerous malfunction. At the default settings, if the RTI frequency were to drop below about 50
Hz, or the background cycle is not performed at least every 512 RTI cycles the timer would trip. The
purpose of this two-part control of the timer is to make sure all aspects of the PMAC software are being
executed, both in foreground (interrupt-driven) and background. If anything keeps either type of routine
from executing, the watchdog will fail quickly.
PLC0 or PLCC0 are meant to be used for only a very few tasks (usually a single task) that must be done
at a higher frequency than the other PLC tasks. The PLC 0 will execute every real-time interrupt as long
as the tasks from the previous RTI have been completed. PLC 0 is potentially the most dangerous task on
PMAC as far as disturbing the scheduling of tasks is concerned. If it is too long, it will starve the
background tasks for time. The first thing to notice is that communications and background PLC tasks
will become sluggish. In the worst case, the watchdog timer will trip, shutting down the card, because the
housekeeping task in background did not have the time to keep it updated.
Although it is very rare for a motion program to cause a watchdog failure, this does happen on occasion.
If there is an empty (no-motion) loop, the motion program acts much like a PLC 0 during this period.
These empty loops, which are used usually to wait for a certain condition, provide fast response to the
change in condition, but their fast repetition occupies a lot of CPU time, and can starve the background
tasks for time. Particularly if several coordinate systems are executing empty loops at the same time,
serious background time limitations can be created which can be severe enough to trip the watchdog
timer.
If there are a huge number of lines of intensive calculations (e.g. 100) before any move or dwell is
encountered, there can be such a long time before background calculations are resumed (more than 512
RTI cycles) it is possible to trip the watchdog timer. If this problem occurs, the calculations should be
split apart with short DWELL commands to give other tasks time to execute.
It is possible to use compiled PLCC programs for faster execution. The faster execution of the compiled
PLCs comes from two factors: first, from the elimination of interpretation time, and second, from the
capability of the compiled PLC programs to execute integer arithmetic. The space dedicated to store up
to 32 compiled PLC programs, however, is limited to 15K (15,360) 24-bit words of PMAC memory; or
14K (14,336) words if there is a user-written servo as well.
In between each scan of each individual background interpreted PLC program, PMAC will execute one
scan of all active background compiled PLCs. This means that the background compiled PLCs execute at
a higher scan rate than the background interpreted PLCs. For example, if there are seven active
background interpreted PLCs, each background compiled PLC will execute seven scans for each scan of a
background interpreted PLC.