Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables 103
If bit 13 (value $2000, or 8,192) is set to 1, when the motor’s following error exceeds the Ixx67 position-
error limit, the excess is put in the “master position” register for the motor, so it is eventually recoverable.
Bit 14: Continue on Desired Position Limit Bit: If bit 14 is set to zero when desired position limits are
enabled (bit 15=1), and desired position within the lookahead buffer exceeds a position limit, Turbo
PMAC will stop execution of the program at the point where the motor reaches the limit.
If bit 14 (value $4000, or 16,384) is set to one when desired position limits are enabled (bit 15=1) (e.g.
I224=$C000) and desired position within the lookahead buffer exceeds a position limit, Turbo PMAC
will continue execution of the program past the point where the motor reaches the limit, but will not let
the desired motor position exceed the limit.
Bit 15: Desired Position Limit Enable Bit: If bit 15 is set to zero, Turbo PMAC does not check to see
whether the desired position for this motor exceeds software overtravel limits.
If bit 15 (value $8000, or 32,768) is set to one (e.g. I324=$8001), Turbo PMAC will check desired
position values for this motor against the software overtravel limits as set by Ixx13, Ixx14, and Ixx41.
If inside the special lookahead buffer, Turbo PMAC will either come to a controlled stop along the path at
the point where the desired position reaches the limit, or continue the program with desired position
saturated at the limit, depending on the setting of bit 14. If not inside the special lookahead buffer, Turbo
PMAC will issue an Abort command when it sees that the desired position has exceeded a position limit.
Bit 16: Amplifier Enable Use Bit: With bit 16 equal to zero – the normal case – the AENAn output is
used as an amplifier-enable line: off when the motor is “killed”, on when it is enabled.
If bit 16 (value $10000, or 65,536) is set to one (e.g. I1924=$10001), this output is not used as an
amplifier-enable line. On PMAC-style channels, it could then be used as a direction output for magnitude
and direction command format if Ixx96 is set to 1. In addition, by assigning an M-variable to the AENAn
output bit, general-purpose use of this output is possible on either Turbo PMAC or PMAC2 if this bit is
set.
Bit 17: Overtravel Limit Use Bit: With bit 17 equal to zero – the normal case – the two hardware
overtravel limit inputs must read 0 (drawing current) to permit commanded motion in the appropriate
direction. If there are not actual (normally closed or normally conducting) limit switches, the inputs must
be hardwired to ground.
If bit 17 (value $20000, or 131,072) is set to one (e.g. I1924=$20000), Motor xx does not use these inputs
as overtravel limits. This can be done temporarily, as when using a limit as a homing flag. If the
hardware overtravel limit function is not used at all, these inputs can be used as general-purpose inputs by
assigning M-variables to them.
Bits 18 and 19: MACRO Node Use Bits: Bits 18 (value $40000, or 262,144) and 19 (value ($80000, or
524,288) of Ixx24 specify what flag information is connected directly to Turbo PMAC hardware
channels, and what information comes through the MACRO ring into a MACRO auxiliary register. The
following table shows the possible settings of these two bits and what they specify:
Bit 19
Bit 18
Capture Flags
Amp Flags
Limit Flags
0
0
Direct
Direct
(don’t care)
0
1
Thru MACRO
Thru MACRO
(don’t care)
1
0
Direct
Thru MACRO
(don’t care)
1
1
Thru MACRO
Direct
(don’t care)
If the amplifier flags are connected through the MACRO ring, bit 23 of Ixx24 must be set to 1 to
designate a high-true amplifier fault, which is the MACRO standard. When using a MACRO auxiliary
register for the flags, Ixx25, Ixx42, or Ixx43 should contain the address of a holding register in RAM, not
the actual MACRO register. Refer to the descriptions of those variables for a list of the holding register
addresses. Turbo PMAC firmware automatically copies between the holding registers and the MACRO
registers as enabled by I70, I72, I74 and I76, for MACRO ICs 0, 1, 2, and 3, respectively. I71, I73, I75,