Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables 217
I7m03 Servo IC m Hardware Clock Control
Range: 0 - 4095
Units: Individual Clock Dividers
I7m03 = Encoder SCLK Divider
+ 8 * PFM_CLK Divider
+ 64 * DAC_CLK Divider
+ 512 * ADC_CLK Divider
where:
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ Encoder SCLK Divider)
PFM_CLK Frequency = 39.3216 MHz / (2 ^ PFM_CLK Divider)
DAC_CLK Frequency = 39.3216 MHz / (2 ^ DAC_CLK Divider)
ADC_CLK Frequency = 39.3216 MHz / (2 ^ ADC_CLK Divider)
Default: 2258 = 2 + (8 * 2) + (64 * 3) + (512 * 4)
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
PFM_CLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
DAC_CLK Frequency = 39.3216 MHz / (2 ^ 3) = 4.9152 MHz
ADC_CLK Frequency = 39.3216 MHz / (2 ^ 4) = 2.4576 MHz
I7m03 controls the frequency of four hardware clock frequencies – SCLK, PFM_CLK, DAC_CLK, and
ADC_CLK – for the four machine interface channels on PMAC2-Style Servo IC m. It is a 12-bit variable
consisting of four independent 3-bit controls, one for each of the clocks. Each of these clock frequencies
can be divided down from a starting 39.3216 MHz frequency by powers of 2, 2
N
, from 1 to 128 times
(N=0 to 7). This means that the possible frequency settings for each of these clocks are:
Frequency
Divide by
Divider N in 1/2
N
39.3216 MHz
1
0
19.6608 MHz
2
1
9.8304 MHz
4
2
4.9152 MHz
8
3
2.4576 MHz
16
4
1.2288 MHz
32
5
614.4 kHz
64
6
307.2 kHz
128
7
Very few Turbo PMAC2 users will be required to change the setting of I7m03 from the default value.
SCLK: The encoder sample clock signal SCLK controls how often Servo IC m’s digital hardware looks
at the encoder and flag inputs. The Servo IC can take at most one count per SCLK cycle, so the SCLK
frequency is the absolute maximum encoder count frequency. SCLK also controls the signal propagation
through the digital delay filters for the encoders and flags; the lower the SCLK frequency, the greater the
noise pulse that can be filtered out. The SCLK frequency should optimally be set to the lowest value that
can accept encoder counts at the maximum possible rate.
PFM_CLK: The pulse-frequency-modulation clock PFM_CLK controls the PFM circuitry that is
commonly used for stepper drives. The maximum pulse frequency possible is 1/4 of the PFM_CLK
frequency. The PFM_CLK frequency should optimally be set to the lowest value that can generate pulses
at the maximum frequency required.
DAC_CLK: The DAC_CLK controls the serial data frequency into D/A converters. If these converters
are on Delta Tau-provided accessories, the DAC_CLK setting should be left at the default value.
ADC_CLK: The ADC_CLK controls the serial data frequency from A/D converters. If these converters
are on Delta Tau-provided accessories, the ADC_CLK setting should be left at the default value.