Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables 251
interpolator diagnostic entry for confirmation of its effect, and to the third line of the interpolator
feedback entry, or the resolver feedback entry, for actual use. The sine bias-correction term is in the high
12 bits (bits 12 – 23); the cosine bias-correction term is in the low 12 bits (bits 0 – 11).
In this mode, the encoder should be moved for several seconds (motion by hand is OK) to ensure good
sampling of maximums and minimums of both waveforms and accurate bias-correction terms. It is
probably best to do this test with the amplifier disabled to prevent the possibility of noise distorting the
maximum and minimum readings.
Byte-Wide Parallel Feedback Entries ($F/$2, $F/$3): An ECT entry in which the first hex digit of the
first line is $F and the first hex digit of the second line is $2 or $3 processes the result of a parallel data
feedback source whose data is in byte-wide pieces in consecutive Y-words. This is used to process
feedback from 3U-format parallel-data I/O boards: the Acc-3E in stack form, and the Acc-14E in pack
(UMAC) form.
Address Word: The first setup line (I-variable) of the entry contains $F in the first hex digit (bits 20-23).
The bit-19 mode-switch bit in the first line controls whether the least significant bit (LSB) of the source
register is placed in bit 5 of the result register (normal shift), providing the standard 5 bits of (non-existent)
fraction, or the LSB is placed in Bit 0 of the result register (unshifted), creating no fractional bits.
Normally, the Bit-19 mode switch is set to 0 to place the source LSB in Bit 5 of the result register. Bit 19
is set to 1 to place to source LSB in Bit 0 of the result register for one of three reasons:
 The data already comes with five bits of fraction, as from a Compact MACRO Station.
 The normal shift limits the maximum velocity too much (V
max
<2
18
LSBs per servo cycle)
 The normal shift limits the position range too much (Range<+2
47
/Ix08/32 LSBs)
Unless this is done because the data already contains fractional information, the unshifted conversion will
mean that the motor position loop will consider one LSB of the source to be 1/32 of a count, instead of one
count.
Bits 0 to 18 of the first line contain the base address of the parallel data to be read. This is the address of
the least significant byte in the parallel feedback word. The following table shows the possible entries
when an Acc-3E stack I/O board is used:
Entry First Lines for Acc-3E 3U-Stack I/O Boards
Acc-3E Address Jumper
E1
E2
E3
E4
First-Line Value
$F7880x
$F7890x
$F78A0x
$F78B0x
The following table shows the possible entries when the Acc-14E UMAC I/O board is used:
Entry First Lines for Acc-14E UMAC I/O Boards
DIP-Switch
Setting
SW1-1 ON (0)
SW1-2 ON (0)
SW1-1 OFF (1)
SW1-2 ON (0)
SW1-1 ON (0)
SW1-2 OFF (1)
SW1-1 OFF (1)
SW1-2 OFF (1)
SW1-3 ON (0)
SW1-4 ON (0)
$F78C0x
$F78D0x
$F78E0x
$F78F0x
SW1-3 OFF (1)
SW1-4 ON (0)
$F79C0x
$F79D0x
$F79E0x
$F79F0x
SW1-3 ON (0)
SW1-4 OFF (1)
$F7AC0x
$F7AD0x
$F7AE0x
$F7AF0x
SW1-3 OFF (1)
SW1-4 OFF (1)
$F7BC0x
$F7BD0x
$F7BE0x
$F7BF0x
A switch that is ON is CLOSED; a switch that is OFF is OPEN.
In both of these tables, the second digit should be changed from a 7 to an F if bit 19 is set to 1 to disable
the data shift.