Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Memory and I/O Map 547
X:$07840E Not used
MACRO IC#
0
1
2
3
Address
$07840F
$07940F
$07A40F
$07B40F
Y:$07x40F MACRO Ring Status and Control (I6840, I6890, I6940, I6990)
Bits: 0 Data overrun error (cleared when read)
1 Byte violation error (cleared when read)
2 Packet parity error (cleared when read)
3 Data underrun error (cleared when read)
4 Master station enable
5 Synchronizing master station enable
6 Sync packet received (cleared when read)
7 Sync packet phase lock enable
8 Node 8 master address check disable
9 Node 9 master address check disable
10 Node 10 master address check disable
11 Node 11 master address check disable
12 Node 12 master address check disable
13 Node 13 master address check disable
14 Node 14 master address check disable
15 Node 15 master address check disable
X:$07x40F MACRO IC clock control register
Bits (Bits 0-11 form I6803 – MACRO IC 0 only)
0-2: Handwheel SCLK* Frequency Control n (f=39.3216MHz/2
n
, n=0-7)
3-5: JHW/PD PFM Clock* Frequency Control n (f=39.3216MHz/2
n
, n=0-7)
6-8: DAC Clock* Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
9-11: ADC Clock* Frequency Control n (f=39.3216MHz / 2
n
, n=0-7)
(Bits 12-13 form I6807, I6857, I6907, I6957)
12: Phase Clock Direction (0=output, 1=input)
(This must be 1)
13: Servo Clock Direction (0=output, 1=input)
(This must be 1)
14-15: Not used (report as zero)
(Bits 16-19 form I6801, I6851, I6901, I6951)
16-19: Phase Clock* Frequency Control n
(f = MAXPHASE* / [n+1], n=0-15)
(Bits 20-23 form I6802 – MACRO IC 0 only)
20-23: Servo Clock* Frequency Control n
(f = PHASE* / [n+1], n=0-15)
Supplemental Servo Channel Registers (MACRO IC 0 only)
Chan #
1*
2*
Address
$078410
$078418
Y:$07841x Handwheel n Time between last two encoder counts (SCLK cycles)
X:$07841x Supplementary Channel n* (Handwheel n) Status Word
Bits: 0-2 Capture Hall Effect Device State
3 Invalid demultiplex of C, U, V, & W
4-6 Reserved for future use (reports as 0)