Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC2 Suggested M-Variable Definitions 611
JTHW Thumbwheel Multiplexer Port M-Variables
M40->Y:$078402,8 ; SEL0 Line; J2 Pin 4
M41->Y:$078402,9 ; SEL1 Line; J2 Pin 6
M42->Y:$078402,10 ; SEL2 Line; J2 Pin 8
M43->Y:$078402,11 ; SEL3 Line; J2 Pin 10
M44->Y:$078402,12 ; SEL4 Line; J2 Pin 12
M45->Y:$078402,13 ; SEL5 Line; J2 Pin 14
M46->Y:$078402,14 ; SEL6 Line; J2 Pin 16
M47->Y:$078402,15 ; SEL7 Line; J2 Pin 18
M48->Y:$078402,8,8,U ; SEL0-7 Lines treated as a byte
M50->Y:$078402,0 ; DAT0 Line; J2 Pin 3
M51->Y:$078402,1 ; DAT1 Line; J2 Pin 5
M52->Y:$078402,2 ; DAT2 Line; J2 Pin 7
M53->Y:$078402,3 ; DAT3 Line; J2 Pin 9
M54->Y:$078402,4 ; DAT4 Line; J2 Pin 11
M55->Y:$078402,5 ; DAT5 Line; J2 Pin 13
M56->Y:$078402,6 ; DAT6 Line; J2 Pin 15
M57->Y:$078402,7 ; DAT7 Line; J2 Pin 17
M58->Y:$078402,0,8,U ; DAT0-7 Lines treated as a byte
M60->X:$078402,0,8 ; Direction control for DAT0 to DAT7
M61->Y:$070800,4 ; Buffer direction control for DAT0 to DAT7, PCbus
M61->Y:$070802,0 ; Buffer direction control for DAT0 to DAT7, VMEbus
M62->X:$078402,8,8 ; Direction control for SEL0 to SEL7
M63->Y:$070800,5 ; Buffer direction control for SEL0 to SEL7, PCbus
M63->Y:$070802,1 ; Buffer direction control for SEL0 to SEL7, VMEbus
Miscellaneous Global Registers
M70->X:$FFFF8C,0,24 ; Time between phase interrupts (CPU cycles/2)
M71->X:$000037,0,24 ; Time for phase tasks (CPU cycles/2)
M72->Y:$000037,0,24 ; Time for servo tasks (CPU cycles/2)
M73->X:$00000B,0,24 ; Time for RTI tasks (CPU cycles/2)
M80->X:$000025,0,24 ; Minimum watchdog timer count
M81->X:$000024,0,24 ; Pointer to display buffer
M82->Y:$001080,0,8 ; First character of display buffer
M83->X:$000006,12,1 ; Firmware checksum error bit
M84->X:$000006,13,1 ; Any memory checksum error bit
M85->X:$000006,5,1 ; MACRO auxiliary communications error bit
M86->X:$000006,6,1 ; Acc-34 serial parity error bit
VME/DPRAM Active Setup Registers
M90->X:$070006,0,8 ; VME Active Address Modifier (Bits 0-7; from I90)
M91->X:$070007,0,8 ; VME Active Address Modifier Don’t Care Bits (Bits 0-7; from I91)
M92->X:$070008,0,8 ; VME Active Base Address Bits A31-A24 (Bits 0-7; from I92)
M93->X:$070009,0,8 ; VME Active Mailbox Base Address Bits A23-A16
; ISA Active DPRAM Base Address bits A23-A16 (Bits 0-7; from I93)
M94->X:$07000A,0,8 ; VME Active Mailbox Base Address Bits A15-A08, ISA Active
; DPRAM Base Address bits A15-A14, Enable & Bank Select
; (Bits 0-7; from I94)
M95->X:$07000B,0,8 ; VME Active Interrupt Level (Bits 0-7; from I95)
M96->X:$07000C,0,8 ; VME Active Interrupt Vector (Bits 0-7; from I96)
M97->X:$07000D,0,8 ; VME Active DPRAM Base Address Bits A23-A20 (Bits 0-7; from I97)
M98->X:$07000E,0,8 ; VME Active DPRAM Enable State (Bits 0-7; from I98)
M99->X:$07000F,0,8 ; VME Active Address Width Control (Bits 0-7; from I99)