Reference Manual
Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables 237
Parallel Feedback Entries ($2, $3, $6, $7): The parallel feedback entries read a word from the address
specified in the low 19 bits (bits 0 to 18) of the first line. The four methods in this class are:
$2: Y-word parallel, no filtering (2-line entry)
$3: Y-word parallel, with filtering (3-line entry)
$6: Y/X-word parallel, no filtering (2-line entry)
$7: Y/X-word parallel, with filtering (3-line entry)
The Bit-19 mode switch in the first line controls whether the least significant bit (LSB) of the source
register is placed in Bit 5 of the result register (normal shift), providing the standard 5 bits of (non-existent)
fraction, or the LSB is placed in Bit 0 of the result register (unshifted), creating no fractional bits.
Normally, the Bit-19 mode switch is set to 0 to place the source LSB in Bit 5 of the result register. Bit 19
is set to 1 to place to source LSB in Bit 0 of the result register for one of three reasons:
The data already comes with five bits of fraction, as from a Compact MACRO Station.
The normal shift limits the maximum velocity too much (V
max
<2
18
LSBs per servo cycle)
The normal shift limits the position range too much (Range<+2
47
/Ix08/32 LSBs)
Unless this is done because the data already contains fractional information, the unshifted conversion will
mean that the motor position loop will consider 1 LSB of the source to be 1/32 of a count, instead of 1
count.
Width/Offset Word: The second setup line (I-variable) of a parallel read entry contains the width of the
data to be read, and the location of the LSB. This 24-bit value, usually represented as 6 hexadecimal digits,
is split evenly into two halves, each of 3 hex digits. The first half represents the width of the parallel data in
bits, and can range from $001 (1 bit wide – not of much practical use) to $018 (24 bits wide).
The second half of the line contains the bit location of the LSB of the data in the source word, and can
range from $000 (Bit 0 of the Y-word at the source address is the LSB), through $017 (Bit 23 of the Y-
word at the source address), and $018 (Bit 24, which is Bit 0 of the next word, is the LSB) to $02F (Bit
47, which is Bit 23 of the next word, is the LSB).
If the LSB bit location exceeds 23, or the sum of the LSB bit location and the bit width exceeds 24, the
source data extends into the next word. If the method character is $2 or $3, the next word is the Y-word
at the source address + 1. If the method character is $6 or $7, the next word is the X-word at the source
address.
For example, to use 20 bits starting at bit 0 (bits 0 – 19) of the Y-word of the source address, this word
would be set to $014000. To use all 24 bits of the X-word of the source address, this word would be set
to $018018. To use 24 bits starting at bit 12 of the specified address (with the highest 12 bits coming
from the X-word or the next higher Y-address, this word would be set to $01800C.
Maximum Change Word: If the method character for a parallel read is $3 or $7, specifying filtered
parallel read, there is a third setup line (I-variable) for the entry. This third line contains the maximum
change in the source data in a single cycle that will be reflected in the processed result, expressed in LSBs
per servo cycle. The filtering that this creates provides an important protection against noise and
misreading of data. This number is effectively a velocity value, and should be set slightly greater than the
maximum true velocity ever expected.
Acc-14: The Accessory 14 family of boards is often used to bring parallel data feedback to the Turbo
PMAC, such as that from parallel absolute encoders, and from interferometers. The following table
shows the first line of the entries for Acc-14D/V boards connected to a Turbo PMAC controller over a
JEXP expansion port cable:
Entries for Acc-14D/V Registers
Register
First Line Value
Register
First Line Value
First Acc-14D/V Port A
$m78A00
Fourth Acc-14D/V Port A
$m78D00
First Acc-14D/V Port B
$m78A01
Fourth Acc-14D/V Port B
$m78D01
Second Acc-14D/V Port A
$m78B00
Fifth Acc-14D/V Port A
$m78E00