Reference Manual

Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Suggested M-Variable Definitions 559
M50->Y:$078801,0,1 ; DAT0 Input
M51->Y:$078801,1,1 ; DAT1 Input
M52->Y:$078801,2,1 ; DAT2 Input
M53->Y:$078801,3,1 ; DAT3 Input
M54->Y:$078801,4,1 ; DAT4 Input
M55->Y:$078801,5,1 ; DAT5 Input
M56->Y:$078801,6,1 ; DAT6 Input
M57->Y:$078801,7,1 ; DAT7 Input
M58->Y:$078801,0,8,U ; DAT0-7 Inputs treated as a byte
Miscellaneous Global Registers
M70->X:$FFFF8C,0,24 ; Time between phase interrupts (CPU cycles/2)
M71->X:$000037,0,24 ; Time for phase tasks (CPU cycles/2)
M72->Y:$000037,0,24 ; Time for servo tasks (CPU cycles/2)
M73->X:$00000B,0,24 ; Time for RTI tasks (CPU cycles/2)
M80->X:$000025,0,24 ; Minimum watchdog timer count
M81->X:$000024,0,24 ; Pointer to display buffer
M82->Y:$001080,0,8 ; First character of display buffer
M83->X:$000006,12,1 ; Firmware checksum error bit
M84->X:$000006,13,1 ; Any memory checksum error bit
M85->X:$000006,5,1 ; MACRO auxiliary communications error bit
M86->X:$000006,6,1 ; Acc-34 serial parity error bit
VME/DPRAM Active Setup Registers
M90->X:$070006,0,8 ; VME Active Address Modifier (Bits 0-7; from I90)
M91->X:$070007,0,8 ; VME Active Address Modifier Don’t Care Bits (Bits 0-7; from I91)
M92->X:$070008,0,8 ; VME Active Base Address Bits A31-A24 (Bits 0-7; from I92)
M93->X:$070009,0,8 ; VME Active Mailbox Base Address Bits A23-A16
; ISA Active DPRAM Base Address bits A23-A16 (Bits 0-7; from I93)
M94->X:$07000A,0,8 ; VME Active Mailbox Base Address Bits A15-A08, ISA Active
; DPRAM Base Address bits A15-A14, Enable and Bank
; Select (Bits 0-7; from I94)
M95->X:$07000B,0,8 ; VME Active Interrupt Level (Bits 0-7; from I95)
M96->X:$07000C,0,8 ; VME Active Interrupt Vector (Bits 0-7; from I96)
M97->X:$07000D,0,8 ; VME Active DPRAM Base Address Bits A23-A20 (Bits 0-7; from I97)
M98->X:$07000E,0,8 ; VME Active DPRAM Enable State (Bits 0-7; from I98)
M99->X:$07000F,0,8 ; VME Active Address Width Control (Bits 0-7; from I99)
Servo IC 0 Registers for PMAC Channel 1 (usually for Motor #1)
M101->X:$078001,0,24,S ; ENC1 24-bit counter position
M102->Y:$078003,8,16,S ; DAC1 16-bit analog output
M103->X:$078003,0,24,S ; ENC1 capture/compare position register
M105->Y:$078006,8,16,S ; ADC1 16-bit analog input
M106->Y:$078000,0,24,U ; ENC1 time between counts (SCLK cycles)
M110->X:$078000,10,1 ; ENC1 count-write enable control
M111->X:$078000,11,1 ; EQU1 compare flag latch control
M112->X:$078000,12,1 ; EQU1 compare output enable
M113->X:$078000,13,1 ; EQU1 compare invert enable
M114->X:$078000,14,1 ; AENA1/DIR1 Output
M116->X:$078000,16,1 ; EQU1 compare flag
M117->X:$078000,17,1 ; ENC1 position-captured flag
M118->X:$078000,18,1 ; ENC1 Count-error flag
M119->X:$078000,19,1 ; ENC1 3rd channel input status
M120->X:$078000,20,1 ; HMFL1 input status