Reference Manual

16-Axis MACRO CPU Hardware Reference Manual
Hardware Memory Map 19
HARDWARE MEMORY MAP
The values in this table represent the hardware locations associated with register-based transactions that
occur in the 16-Axis MACRO CPU.
Reference ADDR (hex) Description
CS00- $FFC0 Stack I/O select #1 (not used with MACRO 16-Axis CPU)
CS02- $FFC8 Stack I/O select #2 (not used with MACRO 16-Axis CPU)
CS04- $FFD0 Stack I/O select #3 (not used with MACRO 16-Axis CPU)
CS06- $FFD8 Stack I/O select #4 (not used with MACRO 16-Axis CPU)
CS0- $C000 Stack axis 1-4 select (not used with MACRO 16-Axis CPU)
CS1- $C020 Stack axis 5-8 select (not used with MACRO 16-Axis CPU)
CS2- $8000 UBUS backplane axis 1-8 select
CS3- $8040 UBUS backplane axis 5-8 select
CS4- $C080 On-board DSPGATE2 select
CS4X- $C0C0 UBUS backplane MACROGATE or DSPGATE2 select (CS4- on UBUS)
CS10- $8800,$9800
$A800,$B800
UBUS backplane I/O select #1
CS12- $8840,$9840
$A840,$B840
UBUS backplane I/O select #2
CS14- $8880,$9880
$A880,$B880
UBUS backplane I/O select #3
CS16- $88C0,$98C0
$A8C0,$B8C0
UBUS backplane I/O select #4
MEMCS0- $D000 UBUS hardware I/O field (was DPRCS-)
MEMCS1- $E000 UBUS hardware I/O field (was VMECS-)
The addressing field size is 16-bits in the 3U 16-Axis MACRO CPU. The address table above is similar
to the PMAC2 product line.