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ADC12EU050

www.ti.com

SNAS444I –JANUARY 2008–REVISED APRIL 2013

ADC12EU050 Ultra-Low Power, Octal, 12-bit, 45 MSPS Sigma-Delta Analog-to-Digital

Converter

Check for Samples: ADC12EU050

FEATURES

DESCRIPTION

The ADC12EU050 is a 12-bit, ultra-low power, octal

• Xignal

™

CT∑Δ ADC Technology

A/D converter for use in high performance analog to

• 45MSPS Sampling Rate

digital applications. The ADC12EU050 uses an

• Anti-Alias Filter Free Nyquist Sample Range

innovative continuous time sigma delta architecture

offering ultra low power consumption and an alias

• Unique Instant Overload Recovery (IOR)

free sample bandwidth up to 22.5MHz. The input

• Wide 2.10 V

Input Range

stage of each channel features a proprietary system

• 1.2V Supply Voltage

to ensure instantaneous recovery from overdrive.

Instant overload recovery (IOR) with no memory

• Integrated Precision LC PLL

effect ensures the elimination of phase errors

• Serial Control via SPI Compatible Interface

resulting from out of range input signals. The

ADC12EU050 reduces interconnection complexity by

APPLICATIONS

using programmable serialized outputs which offer

the industry standard LVDS and SLVS modes. Power

• Medical Imaging, Ultrasound

consumption of only 46mW per channel @ 45MSPS

• Industrial Ultrasound, such as Non-Destructive

gives a total chip power consumption of 364mW. The

Testing

ADC12EU050 can operate entirely from a 1.2V

• Communications

supply, although a separate output driver supply of up

to 1.8V can be used. The device operates from 0 to

• Battery Powered Portable Systems

+70 °C and is supplied in a 10 x 10 mm

, 68-pin

VQFN package.

KEY SPECIFICATIONS

• Resolution 12 Bits

• Conversion Rate 45 MSPS

• SNR : 69.3 dBFS (typ) @ 45 MSPS

= 4.4MHz

• THD –76.6 dB (typ) @ 45 MSPS

= 4.4MHz

• Per Channel Power 46 mW/ch (typ) @ 45 MSPS

• Total Active Power 364 mW (typ) @ 45 MSPS

• Inter-Channel Isolation >110 dB @

= 4.4 MHz

• Operating Temp. Range 0 to +70 °C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 ADC12EU050 Ultra-Low Power, Octal, 12-bit, 45 MSPS Sigma-Delta Analog-to-Digital Converter Check for Samples: ADC12EU050 FEATURES 1 • • • • • • • • 2 ™ Xignal CT∑Δ ADC Technology 45MSPS Sampling Rate Anti-Alias Filter Free Nyquist Sample Range Unique Instant Overload Recovery (IOR) Wide 2.10 VPP Input Range 1.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Block Diagram ADC12EU050 CMOS IN CLK+ (SE) PLL LVDS Input CLK- Output LVDS SLVS BCLK+ BCLK- LC VCO ADC CONTROL SLEEP RST Output LVDS SLVS Register 1.2V VA Register WCLK+ WCLK- AGND 1.2V to 1.8V 1.2V VD DGND DGND Clipping Control VINn+ 12 bit 3 bit 1.3 kÖ Serializer CTÐ? Digital Decimation Filter Modulator VINn- Register Register Register DCAP RREF IRef DOn+ DOn- Register SPI Control To Registers 0.
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ADC12EU050 www.ti.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin No. Name Type Function and Connection Input Differential analog inputs to the ADC, for channels 0 to 7. The negative input pin may be connected via a capacitor to AGND or the inputs may be transformer coupled for single ended operation. Differential inputs are recommended for best performance.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin No. Name Type Function and Connection 38 39 WCLK+ WCLK- Output Word Clock. Differential output frame clock. Information on timing can be seen in ELECTRICAL CHARACTERISTICS. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100 ohm resistors. 44 SDATA Input/Output SPI data input and output.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 OPERATING RATINGS www.ti.com (1) (2) Operating Temperature Range 0°C to +70°C Supply Voltage (VA=VD) +1.16 to +1.26V IO Supply Voltage (VDR) +1.16 to +1.89V Minimum rise time on VA, VD, VDR at power-up 40µs Analog Inputs (VINN+, VINN-) -0.10 to VA SPI Inputs (SDATA, SSEL, SCLK) +1.16 to +2.50V VREFT (When using external reference) 475mV to 525mV VREFB AGND VCM Input Common Mode Range (Differential Input) 0.4V to 1.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 45MHz; fS = 45MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Symbol Typical (1) Limits Units fCLK = 45MHz, fIN = 4.4MHz, VIN = -0.5dBFS 67.6 65.5 dBFS (min) fCLK = 45MHz, fIN = 9.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 45MHz; fS = 45MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 EXTERNAL INPUT CLOCK AND PLL CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 45MHz; fS = 45MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com AC AND TIMING CHARACTERISTICS Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 45MHz; fS = 45MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Symbol Parameter Typical (1) Conditions Limits Units 44.5 MSPS (min) 45.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 AC AND TIMING CHARACTERISTICS (SERIAL INTERFACE) Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL = 5pF; 100Ω terminated at the receiver; fCLK = 45MHz; fS = 45MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com VDR VOCM + VOD/2 Differential output signal VOCM VOCM - VOD/2 0 Figure 3. Output Level Definitions tSCLK tSSELS tSCLKL tWH tSCLKH SCLK SDATA 90% 90% 10% 10% D7 R/W A7 tSSELH tSCLKF tSCLKR tWS D0 SSEL Figure 4. SPI Write Timing tRH tSSELHI tRS A7 , SDATA , SCLK D7 D0 SSEL Figure 5.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC12EU050 employs a number of unique strategies to provide a high performance multi-channel ADC that offers a significant power consumption reduction when compared to compteting architectures, as well as easing system level design. The ultra-low power performance of the ADC12EU050 is derived from the implementation of a fast continuous time sigma delta (CT∑Δ) modulator.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 CLK www.ti.com CLK VIN+ CLK CLK OPAMP VIN- CLK CLK Figure 6. SHA Input Stage VIN+ OPAMP VIN- Figure 7. Continuous Time Sigma Delta Input Stage INSTANT OVERLOAD RECOVERY The ADC12EU050 features an overload handling system which provides instantaneous recovery from signals driving the ADC inputs beyond the full-scale input range. The ADC can operate in two different modes.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 Figure 8. Instant Overload Recovery INTEGRATED PRECISION LC PLL The ADC12EU050 family includes an integrated high performance “clean up” phase locked loop (PLL), simplifying the need for a low jitter external clock.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Such steep digital filters introduce group delay problems, but the ADC12EU050 includes a digital equalizer, which reduces group delay ripple variation to less than 0.05 samples. In applications where group delay is not of concern, the equalizer can be turned off through the SPI interface in order to save power.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 UNCORRELATED NOISE REFERENCE FOR EACH CHANNEL In many early multi-channel ADC designs, a single voltage reference was used to provide the reference level for each channel. Unfortunately, this ensures that the noise at each ADC’s reference terminal is cross correlated. Multi-channel systems often make use of a 3 dB processing gain increase that results from each channel doubling.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com CLOCK SELECTION CONSIDERATIONS The ADC12EU050 has an on-chip PLL, which simplifies the task of clock source selection and clock network design. Clock Input Connection The ADC is designed to accept either single ended or differential clock inputs. Furthermore, the clock source can be a sine or square wave. In order to obtain the best performance, a differential square wave clock should be used.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 ADC INPUT CONSIDERATIONS The ADC12EU050’s sigma delta architecture offers many flexible options for connecting input signals. In order to obtain maximum performance from the device, it is recommended to use a differential input connection. The device, however, also supports single ended analog input. Differential Input Configurations The ADC12EU050 can be driven either actively or passively.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com The ADC12EU050 internally generates a common mode of 0.62V. It is possible to provide input signals with other common modes however, the full scale input range of the ADC must be kept in mind. For this reason, it is recommended that the device inputs are AC coupled. The recommended capacitor value is 100nF.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 VDR = 1.2V VOUT+ Optional internal 1005 termination VOUT- VIN- VIN+ VOCM = 1.0V Bias N Reduced Common Mode LVDS Half Bridge VDD Referenced Figure 17. Output Driver Circuit: Reduced Common Mode LVDS When VDR is 1.8V, the standard LVDS common mode voltage of 1.2V must be used, by setting OCM equal to 1. VDR = 1.8V VOUT+ Bias P Optional internal 1005 termination VOUT- VIN- VIN+ VOCM = 1.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com VDR = 1.2V VOUT+ Bias P Optional internal 1005 termination VOUT- VIN- VIN+ VOCM = 175 mV SLVS Half Bridge VSS Referenced Figure 19. Output Driver Circuit: SLVS As well as the different output modes, the output drive current can also be controlled via the LVDS Control Register. The default output drive current is 2.5mA, but this can be increased to 3.5mA or 5mA, depending on output trace routing and receiver requirements.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 ADC Outputs CH0 Decimator Output Training Sequence 1: 000000111111 CH0 Serializer DO0+ DO0- CH7 Serializer DO7+ DO7- Training Sequence 2: 101010101010 Training Sequence 3: Custom Pattern Serializer Custom Pattern Registers 10h and 11h TSEL[0] TSEL[1] CH7 Decimator Output From Decimator Control Register 16h Figure 20.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com OL should then be set to a value approximately half-way between the new full scale input range (which was just selected by DGF) and the default full scale input range of 2.10Vpp. OL must be set to a value higher than DGF, otherwise the signal will be limited by the analog clipping circuitry, rather than the digtal circuitry, and overload recovery will be impacted.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 DCAP CAPACITOR SELECTION The DCAP pin provides the capacitance for the low pass filter between the DAC bias block and the DAC in the sigma-delta modulator. The filter blocks noise from the DAC Bias block from entering the DAC. Any noise which passes through this filter will be seen in the spectrum as side skirts around the carrier. The filter circuit, which is a first order RC filter, is shown in the diagram below.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com 10 µH 100 nF 100 nF 47 µF 100 nF 100 nF 100 nF 100 nF VDR 47 µF 47 µF 10 µH 10 µH VA VD Transformer drive circuit. Other possible drive circuits shown in Applications Information. 100 nF VA Pins 505 ADT1-6T VCM 100 nF 100 nF 45 MHz clock.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 Programming Guide THE SERIAL CONTROL INTERFACE The ADC12EU050 provides several user controlled functions which are accessed through a standard SPI compatible, 3 wire Serial Interface, as shown in the diagram below. output_enable SPI controller (Master) e.g. DSP, Microcontroller, FPGA serial_out serial_in SDATA clock SCLK chip_select_b SSEL ADC Figure 25.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com SCLK SSEL SDATA A7 A6 A5 A4 A3 A2 A1 R/W D7 SDATA is driven from externally D6 D5 D4 D3 D2 D1 D0 If R/W = 1 (read), the SPI drives SDATA. If R/W = 0 (write), SDATA is driven from externally. Figure 27. Serial Control Interface Protocol The eight address bits, A[7:1] + R/W, are sent first. The data, D[7:0], is then sent for a write transaction, or D[7:0] is received for a read transaction.
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ADC12EU050 www.ti.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Bit Description The SRES is self clearing in approximately 2µs. 2 0 Software Reset Inactive 1 Software Reset Active SPIOD: SPI Open Drain mode. 1 0 Digital Logic Output 1 Open Drain Mode. Enables SPI Driver to operate above VDR SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks. The time to wake-up from sleep mode is < 10µs.
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ADC12EU050 www.ti.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com PLL Control Register • • • Address: 08h Attributes: Write Only Register 09h reads back contents of register 08h b[7] b[6] b[5] 0 0 0 Description b[4] b[3] b[2] 0 0 Reserved Default 0 Bit b[1] b[0] SHBW STCAL 0 0 HEX 00 h Description 7:2 Reserved. Write as zero for future compatibility. 1 SHBW: Set PLL to High Bandwidth.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 Bit Description 2 20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It should be used for an LVDS input clock only. 1 0 Normal operation (10mV hysteresis) 1 20mV hysteresis. (LVDS input clock only) 10HYSOFF: Disable 10mV hysteresis. 10mV hysteresis is the default setting. This bit is used to disable 10mV hysteresis, in the case where another hysteresis setting is desired, for example when using a CMOS input clock.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Decimator Clipping Control Register • • • Address: 14h Attributes: Write Only Register 15h reads back contents of Register 14h Description Default b[7] b[6] CGS Reserved 0 0 b[5] b[4] b[3] b[2] 0 0 a[2:0] 0 b[1] b[0] HEX 0 00 h b[2:0] 0 0 Bit Description 7 CGS: Custom Gain Setting. This bit is used to override the automatic gain settings for ADC and IOR modes.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 Coefficent a[2:0] Coefficent b[2:0] Digital Gain (dB) Equivalent full scale input range (VPP) 010 010 4.16 1.30 010 001 3.95 1.33 010 000 3.74 1.37 010 111 3.52 1.40 010 110 3.29 1.44 001 001 3.06 1.48 001 000 2.82 1.52 001 111 2.58 1.56 001 110 2.33 1.61 000 001 2.07 1.65 000 000 1.80 1.71 000 111 1.53 1.76 000 110 1.24 1.82 111 001 0.95 1.88 111 000 0.64 1.95 111 111 0.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Bit Description 1:0 TSEL[1:0]: Training Sequence Select. These bits select the LVDS output data. The default mode of operation is where the filter output data is serialized. In the remaining modes the selected training sequence is repeatedly output from the serializer this allows the receiving data capture circuitry to perform the de-skewing process.
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ADC12EU050 www.ti.com SNAS444I – JANUARY 2008 – REVISED APRIL 2013 Chip ID Register • • Address: 1Eh Attributes: Read Only b[7] b[6] b[5] b[4] Description b[3] b[2] b[1] b[0] HEX 0 0 0 00 h ID [7:0] Default 0 0 0 0 Bit 7:0 0 Description ID[7:0]: Chip ID Register. Reading from this register will provide the chip version. The expected Chip ID for the ADC12EU050 is 12.4. X = ID[7]*8 + ID[6]*4 + ID[5]*2 + ID[4] Y = ID[3]*8 + ID[2]*4 + ID[1]*2 + ID[0] Chip ID = Version X.
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ADC12EU050 SNAS444I – JANUARY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I • 38 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) ADC12EU050CIPLQ/NOPB ACTIVE Package Type Package Pins Package Drawing Qty VQFN NKE 68 168 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-4-260C-72 HR Op Temp (°C) Device Marking (4/5) -40 to 85 12EU050P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OUTLINE NKE0068A VQFN - 0.9 mm max height SCALE 1.700 PLASTIC QUAD FLATPACK - NO LEAD 10.1 9.9 B A PIN 1 ID 10.1 9.9 0.9 MAX C SEATING PLANE 7.7 0.1 4X (45 X0.42) 18 34 17 35 SYMM 4X 8 1 64X 0.5 0.1 C 0.05 0.00 (0.2) 51 52 68 PIN 1 ID (OPTIONAL) SYMM 68X 0.7 0.5 68X 0.3 0.2 0.1 0.05 C A C B 4214820/A 12/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT NKE0068A VQFN - 0.9 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 7.7) SYMM 68X (0.8) (1.19) TYP 52 68 68X (0.25) 1 51 (1.19) TYP 64X (0.5) SYMM (9.6) ( 0.2) TYP VIA 35 17 34 18 (9.6) LAND PATTERN EXAMPLE SCALE:8X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4214820/A 12/2014 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN NKE0068A VQFN - 0.9 mm max height PLASTIC QUAD FLATPACK - NO LEAD (9.6) (1.19) TYP 68X (0.8) 68 36X ( 0.99) 52 68X (0.25) 1 51 (1.19) TYP 64X (0.5) SYMM (9.6) METAL TYP 35 17 18 34 SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 60% PRINTED SOLDER COVERAGE BY AREA SCALE:8X 4214820/A 12/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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