User`s manual

76 digi.com Multitasking with Dynamic C
If an application uses OSTaskCreateExt, which enables stack checking and allows an extension of the
Task Control Block, fewer parameters are needed in the Rabbit version of µC/OS-II. Using the macros in
the example above, the tasks would be created as follows:
OSTaskCreateExt(task1, NULL, 0, 0, 256, NULL, OS_TASK_OPT_STK_CHK |
OS_TASK_OPT_STK_CLR);
OSTaskCreateExt(task2, NULL, 1, 1, 512, NULL, OS_TASK_OPT_STK_CHK |
OS_TASK_OPT_STK_CLR);
OSTaskCreateExt(task3, NULL, 2, 2, 1024, NULL, OS_TASK_OPT_STK_CHK |
OS_TASK_OPT_STK_CLR);
OSTaskCreateExt(task4, NULL, 3, 3, 2048, NULL, OS_TASK_OPT_STK_CHK |
OS_TASK_OPT_STK_CLR);
OSTaskCreateExt(task5, NULL, 4, 4, 4096, NULL, OS_TASK_OPT_STK_CHK |
OS_TASK_OPT_STK_CLR);
5.10.1.3 Restrictions
At the time of this writing, µC/OS-II for Dynamic C is not compatible with the use of slice statements.
Also, see the function description for OSTimeTickHook() for important information about preserving
registers if that stub function is replaced by a user-defined function.
Due to Dynamic C's stack allocation scheme, special care should be used when posting messages to either
a mailbox or a queue. A message is simply a void pointer, allowing the application to determine its mean-
ing. Since tasks can have their stacks in different segments, auto pointers declared on the stack of the task
posting the message should not be used since the pointer may be invalid in another task with a different
stack segment.
5.10.2 Tasking Aware Interrupt Service Routines (TA-ISR)
Special care must be taken when writing an interrupt service routine (ISR) that will be used in conjunction
with µC/OS-II so that µC/OS-II scheduling will be performed at the proper time.
5.10.2.1 Interrupt Priority Levels
µC/OS-II for the Rabbit reserves interrupt priority levels 2 and 3 for interrupts outside of the kernel. Since
the kernel is unaware of interrupts above priority level 1, interrupt service routines for interrupts that occur
at interrupt priority levels 2 and 3 should not be written to be tasking aware. Also, a µC/OS-II application
should only disable interrupts by setting the interrupt priority level to 1, and should never raise the inter-
rupt priority level above 1.
5.10.2.2 Possible ISR Scenarios
There are several different scenarios that must be considered when writing an ISR for use with µC/OS-II.
Depending on the use of the ISR, it may or may not have to be written so that it is tasking aware. Consider
the scenario in Figure 5-7. In this situation, the ISR for Interrupt X does not have to be tasking aware since
it does not re-enable interrupts before completion and it does not post to a semaphore, mailbox, or queue.