Datasheet

ManualsBrandsDIGILENT ManualsDev Kits210-299

1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

JTAG-HS3™ Programming Cable for Xilinx

FPGAs

Revised June 30, 2014

This manual applies to the JTAG-HS3 rev. A

DOC#: 502-299

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 6

Overview

The JTAG-HS3 programming cable is a high-speed programming/debugging solution for Xilinx FPGAs and SoCs. It is

fully compatible will all Xilinx Tools, and can be seamlessly driven from iMPACT, ChipScope™, EDK, and Vivado™.

The HS3 attaches to target boards using Xilinx’s 2x7, 2mm programming header.

The PC powers the JTAG-HS3 through the USB port and will recognize it as a Digilent programming cable when

connected, even if the cable is not attached to the target board. The HS3 has a separate Vref pin to supply the

JTAG signal buffers. The high speed 24mA three-state buffers allow the HS3 to drive target boards with signal

voltages from 1.8V to 5V and bus speeds up to 30MBit/sec (see Fig. 1). To function correctly, the HS3’s Vref pin

must be tied to the same voltage supply (VCCO_0) that drives the JTAG port on the FPGA.

The JTAG bus can be shared with other devices as the HS3 signals are held in high-impedance, except when

actively driven during programming. The HS3 uses a standard Type-A to Micro-USB cable that attaches to the end

of the module opposite the system board connector. The HS3 is small and light, allowing it to be held firmly in

place by the system board connector (see Fig. 2).

The JTAG-HS3

 Small, complete, all-in-one JTAG

programming/debugging solution for Xilinx FPGAs and

SoCs

 Plugs directly into standard Xilinx JTAG header

 Separate Vref drives JTAG signal voltages; Vref can be

any voltage between 1.8V and 5V

 High-Speed USB2 port that can drive JTAG bus up to

30Mbit/sec (frequency adjustable by user)

 Compatible with Xilinx ISE® 14.1 and newer, Xilinx

Vivado 2013.3 and newer

 Uses micro_AB USB2 connector

 Open drain buffer on pin 14 allows debugging software

to reset the processor core of Xilinx’s Zynq® platform

Figure 2. Xilinx JTAG header. Dual row, 2mm, 14 pin.

Figure 1. Diagram of signal voltages and connections.

: 5V to 1.8V

USB2

Port

TMS

TDI

TDO

TCK

TMS

TDI

TDO

TCK

FPGAJTAG-HS3

GND

VREF

GND

VIO

Features include:

Summary of content (6 pages)

PAGE 1
300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-HS3™ Programming Cable for Xilinx® FPGAs Revised June 30, 2014 This manual applies to the JTAG-HS3 rev. A Overview The JTAG-HS3 programming cable is a high-speed programming/debugging solution for Xilinx FPGAs and SoCs. It is fully compatible will all Xilinx Tools, and can be seamlessly driven from iMPACT, ChipScope™, EDK, and Vivado™. The HS3 attaches to target boards using Xilinx’s 2x7, 2mm programming header.
PAGE 2
JTAG-HS3™ Reference Manual 1 Software Support The JTAG-HS3 has been designed to work seamlessly with Xilinx’s ISE (iMPACT, ChipScope, EDK) and Vivado tool suites. The most recent versions of ISE and Vivado include all of the drivers, libraries, and plugins necessary to communicate with the JTAG-HS3. At the time of writing, the following Xilinx software included support for the HS3: Vivado 2014.1+, Vivado 2013.3+, and ISE 14.1+. The HS3 is also compatible with ISE 13.1 – 13.4.
PAGE 3
JTAG-HS3™ Reference Manual Output Pin (SRST) 100 Figure 5. JTAG-HS3 pin 14 output buffer. Should an accidental short occur between pin 14 and GND, the 100 ohm series resistor protects the buffer from being damaged. While this resistor protects the buffer from being damaged, it also limits the drive strength of the buffer. Therefore, it is necessary for the pull-up resistor (RPU) used to establish the voltage level on PS_SRST_B to be greater than or equal to 1.5K ohms.
PAGE 4
JTAG-HS3™ Reference Manual 3 Supported Target Devices The JTAG-HS3 is capable of targeting the following Xilinx devices:       Xilinx FPGAs Xilinx Zynq-7000 Xilinx CoolRunner™/CoolRunner-II CPLDs Xilinx Platform Flash ISP configuration PROMs Select third-party SPI PROMs Select third-party BPI PROMs The following devices cannot be targeted by the JTAG-HS3:    Xilinx 9500/9500XL CPLDs Xilinx 1700 and 18V00 ISP configuration PROMs Xilinx FPGA eFUSE programming Remote device configuration is not
PAGE 5
JTAG-HS3™ Reference Manual 5 Programming Solutions Comparison Chart JTAG-USB Max Speed Voltage Range Xilinx Native Support Xilinx Plug-in Support Digilent Adept Support PC Interface Connector Interface 4-Wire JTAG 2-Wire JTAG Zynq-7000 PS_SRST Support SPI Support 6 JTAG-HS2 30 MHz JTAG-HS3 1.6 MHz JTAG-HS1 30 MHz 1.8V – 5V 1.8V – 5V 1.8V – 5V 1.8V – 5V ISE 13.2+ Vivado 2014.2+ ISE 13.2+ Vivado 2012.1+ ISE 13.2+ Vivado 2012.1+ ISE 14.1+ Vivado 2013.3+ ISE 12.1+ ISE 12.1+ ISE 12.1+ ISE 12.
PAGE 6
JTAG-HS3™ Reference Manual 7 DC Operating Characteristics Symbol Vref TDO TMS, TCK, TDI Min Typ Max Unit I/O reference/supply voltage 1.65 1.8/2.5/3.3 5.5 Volts Input High Voltage (VIH) 1.4 5.5 Volts Input Low Voltage (VIL) 0 0.45 Volts Output High (VOH) 0.75 x Vref 0.90 x Vref Vref Volts Output Low (VOL) 0 0.05 x Vref 0.15 x Vref Volts 0 0.4 0.55 Volts 70 ºC Output Low (VOL) SRST (RPU = 1.