Datasheet

JTAG-HS3™ Reference Manual

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3 Supported Target Devices

The JTAG-HS3 is capable of targeting the following Xilinx devices:

 Xilinx FPGAs

 Xilinx Zynq-7000

 Xilinx CoolRunner™/CoolRunner-II CPLDs

 Xilinx Platform Flash ISP configuration PROMs

 Select third-party SPI PROMs

 Select third-party BPI PROMs

The following devices cannot be targeted by the JTAG-HS3:

 Xilinx 9500/9500XL CPLDs

 Xilinx 1700 and 18V00 ISP configuration PROMs

 Xilinx FPGA eFUSE programming

Remote device configuration is not supported for the JTAG-HS3 when used with Xilinx’s iMPACT software.

Note: Please see the "Introduction to Indirect Programming – SPI or BPI Flash Memory" help topic in iMPACT for a

list of supported FPGA/PROM combinations.

Note: Please see the “Configuration Memory Support” section of Xilinx UG908 for a list of the FPGA/PROM

combinations that Vivado supports.

4 Design Notes

The JTAG-HS3 uses high speed three-state buffers to drive the TMS, TDI, and TCK signals. These buffers are capable

of sourcing or sinking a maximum of 50 mA of current. The HS3 has 100 ohm resistors between the output of the

buffers and the I/O pins to ensure the cable does not exceed the maximum limit. To further limit short circuit,

additional current resistance may be placed in series with the I/O pins of the HS3 and the target board. However,

Digilent recommends limiting the amount of additional resistance to 100 ohms or less as higher resistance may

result in degraded operation.