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2.7 V to 5.5 V, Serial-Input,

Voltage Output, Unbuffered 16-Bit DAC

AD5541A

Rev. A

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FEATURES

16-bit resolution

11.8 nV/√Hz noise spectral density

1 μs settling time

1.1 nV-sec glitch energy

0.05 ppm/°C temperature drift

5 kV HBM ESD classification

0.375 mW power consumption at 3 V

2.7 V to 5.5 V single-supply operation

Hardware

and

LDAC

functions

50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface

Power-on reset clears DAC output to zero scale

Available in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead

MSOP

APPLICATIONS

Automatic test equipment

Precision source-measure instruments

Data acquisition systems

Medical instrumentation

Aerospace instrumentation

Communications infrastructure equipment

Industrial control

FUNCTIONAL BLOCK DIAGRAMS

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISTER

LOGIC

DGND

DIN

REF

SCLK

LDAC

OUT

AGND

AD5541A

08516-001

CONTROL

LOGIC

Figure 1. AD5541A

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISITER

GND

DIN

REF

CLK

CLR

OUT

AD5541A-1

CONTROL

LOGIC

08516-002

Figure 2. AD5541A-1

GENERAL DESCRIPTION

The AD5541A is a single, 16-bit, serial input, unbuffered voltage

output digital-to-analog converter (DAC) that operates from a

single 2.7 V to 5.5 V supply.

The DAC output range extends from 0 V to V

REF

and is guaranteed

monotonic, providing ±1 LSB INL accuracy at 16 bits without

adjustment over the full specified temperature range of −40°C

to +125°C. The AD5541A is available in a 3 mm × 3 mm, 10-lead

LFCSP and 10-lead MSOP. The AD5541A-1 is available in a

3 mm × 3 mm, 8-lead LFCSP.

Offering unbuffered outputs, the AD5541A achieves a 1 µs set-

tling time with low power consumption and low offset errors.

Providing low noise performance of 11.8 nV/√Hz and low

glitch, the AD5541A is suitable for deployment across multiple

end systems.

The AD5541A uses a versatile 3-wire interface that is compatible

with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface

standards.

Table 1. Related Devices

Part No. Description

AD5040/AD5060

2.7 V to 5.5 V 14-/16-bit buffed output DACs

AD5541/AD5542

2.7 V to 5.5 V 16-bit voltage output DACs

AD5781/AD5791 18-/20-bit voltage output DACs

AD5024/AD5064

4.5 V to 5.5 V, 12-/16-bit quad channel DACs

AD5061 Single, 16-bit nanoDAC, ±4 LSB INL, SOT-23

AD5542A 16-bit, bipolar, voltage output DAC

PRODUCT HIGHLIGHTS

1. 16-bit performance without adjustment.

2. 2.7 V to 5.5 V single operation.

3. Low 11.8 nV/√Hz noise spectral density.

4. Low 0.05 ppm/°C temperature drift.

5. 3 mm × 3 mm LFCSP and MSOP packaging.

Summary of content (21 pages)

PAGE 1
2.7 V to 5.5 V, Serial-Input, Voltage Output, Unbuffered 16-Bit DAC AD5541A FEATURES FUNCTIONAL BLOCK DIAGRAMS 16-bit resolution 11.8 nV/√Hz noise spectral density 1 μs settling time 1.1 nV-sec glitch energy 0.05 ppm/°C temperature drift 5 kV HBM ESD classification 0.375 mW power consumption at 3 V 2.7 V to 5.
PAGE 2
AD5541A* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Designs View a parametric search of comparable parts • CN0169 • CN0181 • CN0348 Evaluation Kits • AD5541A Evaluation Board Reference Materials Documentation Data Sheet • AD5541A: 2.7 V to 5.
PAGE 3
AD5541A TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 14 Applications....................................................................................... 1 Unipolar Output Operation...................................................... 15 Functional Block Diagrams.............................................................
PAGE 4
AD5541A SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C, 1 unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution Relative Accuracy (INL) Max Unit Test Condition Differential Nonlinearity (DNL) ±0.5 ±0.5 ±0.5 ±1.0 ±2.0 ±1.0 Bits LSB LSB LSB B grade A grade Guaranteed monotonic Gain Error 0.5 ±2 ±3 ±4 Gain Error Temperature Coefficient Zero-Code Error ±0.1 0.
PAGE 5
AD5541A AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Reference −3 dB Bandwidth Reference Feedthrough Digital Feedthrough Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ 1 17 1.1 2.2 1 0.2 92 80 74 Max 11.8 0.
PAGE 6
AD5541A TIMING CHARACTERISTICS VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, −40°C < TA < +105°C, unless otherwise noted. Table 4. Parameter 1,2 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t9 t10 t11 t12 2 Limit at 2.7 V ≤ VLOGIC ≤ 5.
PAGE 7
AD5541A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to AGND VLOGIC to DGND Digital Input Voltage to DGND VOUT to AGND AGND to DGND Input Current to Any Pin Except Supplies Operating Temperature Range Industrial (A, B Versions) Storage Temperature Range Maximum Junction Temperature (TJ max) Package Power Dissipation Thermal Impedance, θJA LFCSP (CP-10-9) LFCSP (CP-8-11) MSOP (RM-10) Lead Temperature, Soldering Peak Temperature1 ESD2 1 2 Rating −0.3 V to +6 V −0.
PAGE 8
AD5541A 10 VLOGIC VOUT 2 VDD 1 AD5541A 9 DGND AGND 3 TOP VIEW (Not to Scale) 8 LDAC 7 DIN 6 SCLK REF 4 CS 5 08516-031 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. AD5541A 10-Lead MSOP Pin Configuration Table 6. AD5541A Pin Function Descriptions 1 2 3 4 Pin No. Mnemonic VDD VOUT AGND REF 5 6 CS SCLK 7 DIN 8 LDAC 9 10 DGND VLOGIC Description Analog Supply Voltage. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry.
PAGE 9
AD5541A SCLK 3 AD5541A AGND 3 TOP VIEW (Not to Scale) 7 VDD TOP VIEW (Not to Scale) 6 VOUT REF 4 5 CLR CS 5 DIN 4 NOTES 1. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, GND. 10 VLOGIC VOUT 2 AD5541A-1 9 DGND 8 LDAC 7 DIN 6 SCLK NOTES 1. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, GND.
PAGE 10
AD5541A TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 DIFFERENTIAL NONLINEARITY (LSB) 0 –0.25 –0.50 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE 0 –0.25 –0.50 08516-006 –0.75 0.25 0 8192 Figure 7. Integral Nonlinearity vs. Code 0.75 0 –0.25 –0.50 –1.00 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 0.50 0.25 0 –0.25 –0.50 –60 08516-007 –0.75 VDD = 5V VREF = 2.5V Figure 8. Integral Nonlinearity vs.
PAGE 11
AD5541A 1.5 3 VDD = 5V VREF = 2.5V TA = 25°C 1.0 ZERO-CODE ERROR (LSB) 1 0 –1 0.5 0 –0.5 –1.0 –2 –50 0 50 TEMPERATURE (°C) 100 150 –1.5 –55 08516-012 –3 –100 Figure 13. Gain Error vs. Temperature 45 TEMPERATURE (°C) 95 Figure 16. Zero-Code Error vs. Temperature 200 160 TA = 25°C VDD = 5V VREF = 2.5V TA = 25°C 140 120 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) –5 08516-015 GAIN ERROR (LSB) 2 VDD = 5V VREF = 2.
PAGE 12
AD5541A VREF = 2.5V VDD = 5V TA = 25°C VREF = 2.5V VDD = 5V TA = 25°C 100 • • • • 100 DIN (5V/DIV) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • VOUT (1V/DIV) 90 VOUT (50mV/DIV) GAIN = –216 1LSB = 8.2mV VOUT (50mV/DIV) 10 10 0% • • • • • • • • • • • • • • • • • • • • • • • • 08516-018 0% 2µs/DIV • • • • • • • • • • • • • • • • 08516-021 90 0.5µs/DIV Figure 19. Digital Feedthrough Figure 22. Small Signal Settling Time 5 1.
PAGE 13
AD5541A 40 10 0 5 VOUT (dBm) OUTPUT NOISE (µV rms) 20 –20 –40 0 –60 0 20 40 60 80 FREQUENCY (Hz) 100 120 –100 08516-033 –5 0 40 10 35 0 30 30,000 40,000 50,000 FREQUENCY (Hz) 60,000 70,000 VOUT/VREF (dBm) –10 25 20 15 –20 –30 –40 10 700 800 900 1000 1100 FREQUENCY (Hz) 1200 1300 1400 –60 1k Figure 26. Noise Spectral Density vs.
PAGE 14
AD5541A TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity.
PAGE 15
AD5541A THEORY OF OPERATION The AD5541A is a single, 16-bit, serial input, voltage output DAC. It operates from a single supply ranging from 2.7 V to 5 V and consumes typically 125 μA with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, this part is designed with a power-on reset function. The output is reset to 0 V. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections.
PAGE 16
AD5541A UNIPOLAR OUTPUT OPERATION OUTPUT AMPLIFIER SELECTION This DAC is capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply current, typically 300 μA, and a low offset error. The AD5541A provides a unipolar output swing ranging from 0 V to VREF − 1 LSB. Figure 31 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 8. The example includes the ADR421 2.
PAGE 17
AD5541A FORCE SENSE AMPLIFIER SELECTION POWER-ON RESET Use single-supply, low noise amplifiers. A low output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to ±20 mA. The AD5541A has a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register.
PAGE 18
AD5541A APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5541A is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5541A requires a 16-bit data-word with data valid on the rising edge of SCLK.
PAGE 19
AD5541A DECODING MULTIPLE DACS AD5541A SCLK The CS pin of the AD5541A can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device receives the CS signal at any one time. The DAC addressed is determined by the decoder. There is some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 35 shows a typical circuit.
PAGE 20
AD5541A OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 36. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 10 1.74 1.64 1.49 EXPOSED PAD 0.
PAGE 21
AD5541A 2.44 2.34 2.24 3.10 3.00 SQ 2.90 0.50 BSC 8 5 0.50 0.40 0.30 1 4 BOTTOM VIEW TOP VIEW 0.80 0.75 0.70 SEATING PLANE 1.70 1.60 1.50 EXPOSED PAD 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED 01-24-2011-B PIN 1 INDEX AREA Figure 38.