300 Henley Court Pullman, WA 99163 509.334.6306 www.store.digilent.com Genesys 2 FPGA Board Reference Manual Revised August 24, 2017 This manual applies to the Genesys 2 rev. F Overview The Digilent Genesys 2 board is an advanced, high-performance, ready-to-use digital circuit development platform based on the latest Kintex-7™ Field Programmable Gate Array (FPGA) from Xilinx.
Genesys 2 FPGA Board Reference Manual The Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash, or the on-board USB-JTAG programmer circuit. The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset. Included in the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2. This allows designs to be implemented straight out of the box at no additional cost.
Genesys 2 FPGA Board Reference Manual Callout Component Description Callout Component Description 8 JTAG header 21 VGA connector 9 User slide switches 22 HDMI source connector 10 User LEDs 23 FPGA configuration source jumper 11 OLED display 24 HDMI sink connector 12 Dual analog/digital Pmod 25 Power switch 13 User pushbuttons 26 Power jack 12VDC Table 1.
Genesys 2 FPGA Board Reference Manual All Genesys 2 power supplies can be turned on and off together by a single logic-level power switch (SW8). Power supplies are either enabled/disabled directly by the power switch or indirectly by other supplies upstream. A power-good LED (LD15), driven by the “power good” output of the on-board regulators, indicates that the supplies are turned on and operating normally. An overview of the Genesys 2 power circuit is shown in Figure 1.
Genesys 2 FPGA Board Reference Manual Supply Circuits Device Current (max/typical) 3.3 V FPGA I/O, USB, FMC, Clocks, Pmod, Ethernet, SD slot, Flash, DisplayPort, HDMI IC42: LTC3855#1 6 A / 0.8 A 1.0 V FPGA Core IC30: LTC3866 14 A / 1.2 A 1.8 V FPGA Auxiliary IC36: LTC3605 5 A / 1.6 A 1.5 V DDR3 and FPGA I/O IC32: LTC3618 2 A / 0.7 A 0.75V DDR3 termination, reference IC32: LTC3618 2A 2.0 V FPGA Auxiliary I/O for memory high data rates3 IC38: LT1762 150 mA VADJ (1.2-3.
Genesys 2 FPGA Board Reference Manual 3 Power monitoring I2C-interfaced monitoring circuits, INA219 from Texas Instruments, are available on the main power rails. These allow real-time voltage, current, and power readings in the FPGA. Six such circuits share the same I2C bus with different slave addresses. These are summarized in Table 3, along with recommended configuration values.
Genesys 2 FPGA Board Reference Manual 4 Fan The Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan is powered from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN_EN” signal. Pulling the signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default. Feedback is obtained on the “FAN_TACH” signal.
Genesys 2 FPGA Board Reference Manual Micro-B USB Connector (J17) 6-pin JTAG Header (J19) USB Controller JTAG Port 1x6 JTAG Header SPI quad-mode Flash Mode (JP5) Kintex-7 M0 M2 M1 Micro SD Connector (J3) Type A USB Host Connector (J7-top) SPI Port User I/O DONE 2 PIC24 Slave Serial PROG_B JP4 JP5 any Flash any JTAG USB microSD Programming Mode Media Select (JP4) Figure 5. Genesys 2 Configuration Options. The FPGA configuration data is stored in files called bitstreams that have the .
Genesys 2 FPGA Board Reference Manual the onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2, attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on, regardless of what the mode jumper (JP5) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG.
Genesys 2 FPGA Board Reference Manual 6. Push the PROG button or power-cycle the Genesys 2. The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Kintex-7 device will be rejected by the FPGA.
Genesys 2 FPGA Board Reference Manual Setting Data mask Input clock period Output driver impedance Chip Select pin Rtt (nominal) – On-die termination Internal Vref Reference clock Internal termination impedance DCI cascade Value Enabled 5004ps (~200MHz) RZQ/7 Enabled RZQ/6 Disabled Use system clock N/A Disabled Table 4. DDR3 Settings for the Genesys 2. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core.
Genesys 2 FPGA Board Reference Manual SPI Flash Kintex-7 CS# SDI/DQ0 SDO/DQ1 WP#/DQ2 HLD#/DQ3 SCK SPI Flash U19 P24 R25 R20 R21 N/A* *SCK Is only available via the STARTUPE2 primitive Figure 6. Genesys 2 SPI Flash pin-out. 7 Ethernet PHY The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management.
Genesys 2 FPGA Board Reference Manual On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC address pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash8. This unique identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique MAC to allow connecting several Genesys 2 boards to the same network.
Genesys 2 FPGA Board Reference Manual clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” (ug47210) available from Xilinx. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user.
Genesys 2 FPGA Board Reference Manual controller. One port is used exclusively for JTAG, while the other either DPTI or DSPI. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. Micro-USB (J17) JTAG JTAG D0/SCK D1/MOSI D2/MISO D3/SS D4 D5 D6 D7 RXF# TXE# RD# WR# SIWU# OE# CLKOUT SPIEN AD27 W27 W28 W29 Y29 Y28 AA28 AA26 AB29 AA25 AB25 AC27 AB28 AC30 AB27 AD29 FT2232H Kintex-7 Figure 9. USB-FPGA interfaces provided by the USB JTAG port. 10.
Genesys 2 FPGA Board Reference Manual For more information, see the FT2232H data sheet 11. 10.2 Serial Peripheral Interface (DSPI) An industry-standard SPI interface can also be used for transferring data. It uses only four signals for serial fullduplex communication. The USB controller acts as a SPI master, with the FPGA taking the slave role. The USB controller initiates a transaction after API function calls and transfers data in both directions simultaneously.
Genesys 2 FPGA Board Reference Manual 11.1 HID Controller The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host.
Genesys 2 FPGA Board Reference Manual ESC 76 `~ 0E 1! 16 TAB 0D F1 05 F2 06 F3 04 F4 0C 2@ 1E 3# 26 4$ 25 5% 2E Q 15 Caps Lock 58 W 1D A 1C Shift 12 S 1B Z 1Z Ctrl 14 E 24 R 2D D 23 X 22 F5 03 6^ 36 T 2C F 2B C 21 Alt 11 F7 83 7& 3D Y 35 G 34 V 2A F6 0B 8* 3E U 3C H 33 B 32 F8 0A 9( 46 I 43 J 3B N 31 F9 01 0) 45 O 44 K 42 M 3A F10 09 -_ 4E P 4D L 4B ,< 41 =+ 55 [{ 54 ;: 4C >. 49 Space 29 /? 4A Alt E0 11 F11 78 F12 07 BackSpace 66 ]} 5B '" 52 \| 5D Enter 5A Shi
Genesys 2 FPGA Board Reference Manual generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred).
Genesys 2 FPGA Board Reference Manual Auxiliary circuitry, like an electronic power switch and jumpers are used to implement different USB roles. In Host applications, the switch can be commanded through the PHY to power VBUS. The switch has built-in current limit and short circuit protection. VBUS error conditions are signaled to the FPGA by means of a status pin. In Device role, this switch should be disabled.
Genesys 2 FPGA Board Reference Manual VADJ M20 BTNL Buttons C19 BTNR B19 BTNU M19 BTND E18 BTNC LD0 T28 V19 U30 U29 V20 V26 W24 W23 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LEDs VADJ Slide Switches VCC3V3 SW0 G19 SW1 G25 SW2 H24 SW3 K19 SW4 N19 SW5 P19 SW6 P26 SW7 P27 3.3V R19 BTN1 CPU Reset Kintex-7 Figure 15. General purpose I/O connections.
Genesys 2 FPGA Board Reference Manual Table 10 summarizes these differences. Pmod Connector Power Analog/Digital JXADC VADJ Dual JA, JB 3.3 V Digital-only JC, JD 3.3 V Digital-only Routing Differential; Pairs: 1-7,2-8,3-9,4-10 Differential; Pairs: 1-2,3-4,7-8,9-10 Single-ended Series protection Recommended usage 100 ohm Analog inputs; LVDS_25 input/output (VADJ=2.5V) 0 ohm >=10MHz; LVDS_25 input 200 ohm <10 MHz, LVCMOS33 Table 10. Pmod differences.
Genesys 2 FPGA Board Reference Manual NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals. The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP).
Genesys 2 FPGA Board Reference Manual Quad Primitive 115 GTXE2_CHANNEL X0Y0 X0Y1 X0Y2 X0Y3 Pin type MGTXTXP/N0 MGTXRXP/N0 MGTXTXP/N1 MGTXRXP/N1 MGTXTXP/N2 MGTXRXP/N2 MGTXTXP/N3 MGTXRXP/N3 Pin Y2/Y1 AA4/AA3 V2/V1 Y6/Y5 U4/U3 W4/W3 T2/T1 V6/V5 FMC signal DP0_C2M_P/N DP0_M2C_P/N DP1_C2M_P/N DP1_M2C_P/N DP2_C2M_P/N DP2_M2C_P/N DP3_C2M_P/N DP3_M2C_P/N P2/P1 T6/T5 N4/N3 R4/R3 M2/M1 P6/P5 L4/L3 M6/M5 FMC signal DP4_C2M_P/N DP4_M2C_P/N DP5_C2M_P/N DP5_M2C_P/N DP6_C2M_P/N DP6_M2C_P/N DP7_C2M_P/N DP7_M2C_P/N
Genesys 2 FPGA Board Reference Manual To talk to an SD card, several communication layers need to be implemented in the FPGA. The physical layer (de)serializes command and data packets over either the SD native or SPI interface. The data link layer should implement the SD state machine, issuing initialization and read/write commands specific to the SD standard. The data link layer provides access to raw blocks/sectors on the SD card.
Genesys 2 FPGA Board Reference Manual 5V0 Powered from 5V rail Powers auxiliary signals Figure 18. HDMI pin description and assignment. 13.1 TMDS signals HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS). To make proper use of either of the HDMI ports a standard-compliant transmitter or receiver needs to be implemented in the FPGA. The implementation details are outside the scope of this manual. 13.
Genesys 2 FPGA Board Reference Manual The auxiliary channel is a bidirectional channel for link management and device control. It is AC-coupled, just like the main link lanes, but uses a different encoding and the lower data rate of 1Mbps. Upon hot-plug detection a Source will attempt to configure the link through link training. Handshaking link parameters happens via the auxiliary channel. Genesys 2 includes two Mini DisplayPort (mDP) connectors: one wired as Source, the other as Sink.
Genesys 2 FPGA Board Reference Manual Lane 3 MGTXRXP/N3 Lane 2 MGTXRXP/N2 Lane 1 MGTXRXP/N1 Lane 0 MGTXRXP/N0 MGTXTXP/N3 MGTXTXP/N2 MGTXTXP/N1 Lane 3 Lane 1 Lane 0 MGTXTXP/N0 MGTREFCLK0P/N mDP Sink Lane 2 Osc 135 MHz mDP Source MGT 118 Kintex-7 AD17 AD16 AA18 AB18 AD21 Y19 Y18 AB19 AC19 AE21 AUX_P AUX_N HPD AUX_P AUX_N HPD Figure 19. DisplayPort wiring diagram. The full implementation details of the DisplayPort standard is outside the scope of this document.
Genesys 2 FPGA Board Reference Manual The serial interface is synchronous to SCLK and must conform the timing specifications below. In most cases, a 10 MHz SCLK and data sent on the falling edge should work. Figure 20. Serial interface timing diagram. Start-up sequence: 1. 2. 3. 4. 5. Power up VDD by pulling OLED_VDD low. Wait 1ms. Pulse RES# low for at least 3us. Power up VBAT by pulling OLED_VBAT low. Wait 100ms for voltage to stabilize. Clear screen by writing zero to the display buffer.
Genesys 2 FPGA Board Reference Manual Command function Column inversion disable Scan direction COM pins configuration Addressing mode: horizontal Command bytes 0xA0 0xC0 0xDA, 0x00 0x20 Table 17. OLED configuration commands. After start-up, writing to the display is done by sending data bytes over the serial interface (D/C# high). Each data bit corresponds to a pixel, with the addressing mode, inversion and scan direction settings determining exactly which.
Genesys 2 FPGA Board Reference Manual 1. 2. 3. Provide MCLK for the audio codec. Use an I2C master controller to configure the core clocking, sample rates, serial interface format and audio path. Send or receive audio samples over the serial audio data channel for playback or record. More advanced users might want to try additional features of the ADAU1761. For example, the on-chip SigmaDSP core can be programmed to do user-defined digital signal processing.
