CMOS 4-bit Single Chip Microcomputer Core CPU Manual

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 41
3 INSTRUCTION SET
INC Mn Increment memory by 1
HALT Halt
HALT
Stops CPU
111111111000 FF8H
VI
5
Not affected
Not affected
Not affected
Not affected
Stops the CPU. When an interrupt occurs, PCP and PCS are pushed onto the
stack as the return address and the interrupt service routine is executed.
Instruction State PCP PCS I flag
HALT RUN 0001 0011 0011 1
HALT
Interrupt 0001 0011 0100 1
RUN 0001 Interrupt vector address 0
INC Mn
M(n
3 to n0) ← M(n3 to n0) + 1
11110110n
3 n2 n1 n0 F60H to F6FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
The contents of the data memory location addressed by Mn is incremented by 1.
INC M1 INC M3 INC M0DH
Memory (01H) 0100 0101 0101 0101
Memory (03H) 1111 1111 0000 0000
Memory (0DH) 0111 0111 0111 1000
C flag 0 0 1 0
Z flag 1 0 1 0