CMOS 4-bit Single Chip Microcomputer Core CPU Manual

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
66 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
POP YH Pop stack data into YH
POP YH
YH ← M(SP), SP ← SP + 1
11111101 1 000 FD8H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into YH, the four high-order bits of Y. SP is incremented by 1.
POP YH
SP C1 C2
Memory (C1H) 1101 1101
YH register 0010 1101
POP YL Pop stack data into YL
POP YL
YL ← M(SP), SP ← SP + 1
11111101 1 001 FD9H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into YL, the four low-order bits of Y. SP is incremented by 1.
POP YL
SP CA CB
Memory (CAH) 0100 0100
YL register 0101 0100
2
3
2
2
2
1
2
0
M(SP) =
= YH
2
0
2
1
2
2
2
3
2
3
2
2
2
1
2
0
M(SP) =
= YL
2
0
2
1
2
2
2
3