Specifications

4–36 EPSON
SED1220
(3) Serial Interface
t CSS t CSH
t SAS t SAH
t SLW
t SCYC
t SHW
t SDS t SDH
CS
A0
SCL
SI
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
V SS × 0.8 [V]
V
SS × 0.2 [V]
t r t f
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System clock cycle SCL t
SCYC Every timing is specified 1000 ns
SCL “H” pulse width t
SHW on the basis of 20% and 300 ns
SCL “L” pulse width t
SLW 80% of VSS. 300 ns
Address setup time A0 t
SAS 50 ns
Address hold time t
SAH 300 ns
Data setup time SI t
SDS 50 ns
Data hold time t
SDH 50 ns
CS-SCL time CS t
CSS 150 ns
t
CSH 700 ns
[Ta = –30 to 85°C, VSS = –3.6 V to –2.4 V]