Specifications
5–10 EPSON
SED1225 Series
Figure 1
Data bus signal identification
The SED1225 identifies the data bus based on a
combination of A0, AWR and E signals as defined on
Table 3.
Table 3
Chip Select
The SED1225 has an Chip Select pin (XCS) to allow an
MPU interface input only if XCS=low.
During no chip select status, all of D0 to D7, A0, XWR,
SI and SCL inputs are made invalid. If the serial input
interface is selected, the shift register and counter are
reset.
However, the Reset signal is entered independent from
the XCS status.
Power Circuit
The built-in power circuit featuring the low power
consumption generates the required LCD drive voltages.
The power circuit consists of an amp and a voltage
regulator.
Amp
When the capacitors are connected to the OCA, OCB,
OCC, OCD, OCE, V
REG2 pins, the LCD drive voltages
are generated.
As the amp uses the signals from the oscillator, the
oscillator or an external clock must be operating.
The following provides the potential relationship.
SCL 1
A0
SI
XCS
D7 D6 D5 D4 D3 D2 D1 D0 D7
2345678
A0
1
Common 68 Series 80 Series
Function
A0 E XWR
1 1 0 Writes in the RAM and symbol register.
0 1 0 Writes (commands) in the internal register.
LEC drive voltages
V
0
= V
DD
V
1
V
2
, V
3
V
4
V
5
V
REG2
V
5
= 4 x V
REG2
Voltage
drop
Voltage rise
V
DD
= 0V
V
SS