Specifications

5–30 EPSON
SED1225 Series
(3) Serial interface
*1 The input signal rise and fall times (tr, tf) are defined to be 25 nsec max (except for RES input).
t CSS t CSH
t SAS t SAH
t SLW
t SCYC
t SHW
t SDS t SDH
XCS
A0
SCL
SI
V SS x 0.8 [V]
V
SS x 0.2 [V]
t r t f
(Ta = –30 to +85°C, VSS = –3.6V to –1.7V)
Item Signal Symbol Conditions Min. Max. Unit
System clock cycle
tSCYC 3000 —
SCL "Hi" pulse width SCL
tSHW 2850 — ns
SCL "Lo" pulse width tSLW 150 —
Address setup time
A0
tSAS
All timing must be based on
50 —
Address hold time tSAH
20% and 80% of VSS.
800 —
ns
Data setup time
SI
tSDS 50 —
Data hold time tSDH 50 —
ns
CS-to-SCL time XCS
tCSS 400 —
tCSH 2500 —
ns
(Ta = –30 to +85°C, VSS = –3.3V to –2.7V)
Item Signal Symbol Conditions Min. Max. Unit
System clock cycle
tSCYC 1400 —
SCL "Hi" pulse width SCL
tSHW 1300 — ns
SCL "Lo" pulse width tSLW 50 —
Address setup time
A0
tSAS
All timing must be based on
50 —
Address hold time tSDH
20% and 80% of VSS.
500 —
ns
Data setup time
SI
tSDS 30 —
Data hold time tSDH 30 —
ns
CS-to-SCL time XCS
tCSS 200 —
tCSH 1500 —
ns