Specifications

EPSON 2–9
SED1200 Series
SED1200
Series
VDD = 3 V
VSS = 0 V, Ta = –10 to 70°C
Parameter Symbol Condition
Rating
Unit Pin
min typ max
Logic supply voltage VDD 2.5 3.5 4.5 V VDD
Liquid crystal display supply
V
LCD VDD–5.5 VDD–3.5 V VLCD
voltage
Oscillator feedback resistor Rf VDD = 3.0 V, fOSC = 100 kHz 210 290 370 k XG, XD
Operating frequency (1)
oscillator or external clock fOSC VDD = 2.5 V 300 kHz XG, XD
frequency
Operating frequency (2) Φ VDD = 2.5 V 1.0 MHz Φ
External clock duty VDD = 2.5v 50 % OSC1, Φ
External clock rise time tr VDD = 2.5 V 50 ns OSC1, Φ
External clock fall time tf VDD = 2.5 V 50 ns OSC1, Φ
H-level input voltage (1) VIH1 VDD = 2.5 V 0.8 VDD —VDD V CS, RD, WR,
L-level input voltage (1) VIL1 VDD = 2.5 V 0 0.2 VDD V DB0 to DB3, Φ
H-level input voltage (2) VIH2 VDD = 2.5V 0.8 VDD ——V
X
G
L-level input voltabe (2) VIL2 VDD = 2.5 V 0.2 VDD V
H-level input leakage current ILIH VDD = 4.5 V |–1.0| µA Φ, XG,
L-level input leakage current ILIL VDD = 4.5 V 1.0 µA DB0 to DB3
Input pull-up current IIPU VDD = 3.5 V 1.0 4.0 15 µA CS, RD, WR, A0
H-level output current IOH VDD = 2.5 V, VOH = 2.0 V 200 µA
DB3
L-level output current IOL VDD = 2.5 V, VOL = 0.5 V 200 µA
Common driver output current (1) IOH VDD level |-20| µA
Common driver output current (2) IOL VLCD level 20 µA
COM1 to COM16
Common driver output current (3) IOL VL1 level |±8| µA
Common driver output current (4) IOL VL4 level |±8| µA
Segment drivrer output current (1) IOH VDD level |–12| µA
Segment drivrer output current (2) IOL VLCD level 12 µA
SEG1 to SEG50
Segment drivrer output current (3) IOL VL2 level |±4| µA
Segment drivrer output current (4) IOL VL3 level |±4| µA
Voltage-divider resistor (1) Rd1 Normal conditions 130 k
Voltage-divider resistor (2) Rd2 Low impedance state 13 k
Voltage-divider resistor low
tRd1/tRd2
1/8 Duty 11/400
impedance duty
1/16 Duty 11/200
Command execution time tcomd
From WR rise time to the
——
16/Φ
µs
end of internal processing (MHz)
V
DD–VSS = 3.5 V
VDD–VLCD = 1.5 V
Average operating current I
DD fOSC = 100 kHz, Φ = 500 kHz 60 µAVDD
CS = RD = WR = A0 = VDD,
output open
VDD–VLCD = 3.5 V
Voltage-divider
resistor in low
impedance state.
1/16 duty
0.5 V voltage drop
Measured on one
pin with other pins
open circuit.