Specifications

6–2 EPSON
SED1230 Series
BLOCK DIAGRAM
D6 (SCL)
Input buffer
MPU interface
Address counter
Command
decoder
Cursor control
SEG driving circuit COM driving circuit
Refresh address counter
RAM
DD RAM
CG RAM
CG ROM
Timing generating circuit
Oscillator
Power circuit
D0 D1 D2 D3 D4 D5 D7 (SI)
IF
RES
CS
WR (E)
P/S
A0
SEG1~60 SEGS1~6
COM1~28 COMS1~3
V
1
V
2
V
3
V
4
V
5
CAP1+ CAP1– CAP2+ CAP2– V
R
V
OUT
V
S1