Specifications
6–34 EPSON
SED1230 Series
*5: Character “ ” display. This is applicable to the
case where no access is made from the MPU and the
built-in power circuit and oscillating circuit are in
operation.
*6: This is applicable to the case where the built-in power
circuit is OFF and the oscillating circuit is in opera-
tion in the standby mode.
*7: Current consumption when data is always written by
f
cyc.
The current consumption in the access state is almost
proportional to the access frequency (f
cyc).
When no access is made, only I
DD (I) occurs.
*8:
tR (reset time) indicates the internal circuit reset
completion time from the edge of the RES signal.
Accordingly, the SED123
*
usually enters the oper-
ating state after
tR.
*9: Specifies the minimum pulse width of the RES
signal. It is reset when a signal having the pulse
width greater than
tRW is entered.
*10:When operating the boosting circuit, the power
supply V
SS must be used within the input voltage
range.
*11:The fOSC frequency of the oscillator circuit for
internal circuit drive may differ from the fBST boost-
ing clock on some models. The following provides
the relationship between the f
OSC frequency, fBST
boosting clock, and fFR frame frequency.
f
OSC = (No. of digits) × (1/Duty) × fFR
fBST = (1/2) × (1/No. of digits) × fOSC
Example: The SED1230 has 13 digits of display
and 1/30 duty.
f
OSC = 13 × 30 × 100 = 39 kHz
f
BST = (1/2) × (1/13) × 39 K = 1.5 kHz
*12:The V
REG reference voltage has the temperature
characteristics of approximately –0.17%/°C (stand-
ard specifications). An optional model having the
temperature characteristics of approximately
–0.04%/°C is also available. The voltage of power
supply terminal V
SS can be selected as the reference
power supply as an option without using the refer-
ence voltage inside the IC. In this case, however, a
regulator is used for the external power supply (V
DD
– VSS). The voltage accuracy of V5 depends on that
of the regulator used. The CGROM modification
rules apply to the optional models.
Power Supply
t
RES
V
DD
V
SS
V
DD
V
SS
–2.4 V
t
RW
t
R
RES
All signal timings are based on 20% and 80% of V
SS
signals.