Specifications

SED1230
Series
EPSON 6–37
SED1230 Series
(3) Serial Interface
*1: For the rise and fall of an input signal, set a value not exceeding 25 ns.
*2: Every timing is specified on the basis of 20% and 80% of V
SS.
t CSS t CSH
t SAS t SAH
t SLW
t SCYC
t SHW
t SDS t SDH
CS
A0
SCL
SI
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System clock cycle SCL t
SCYC VSS = –3.0 700 ns
–2.7 800 ns
–2.4 1000 ns
SCL “H” pulse width t
SHW 300 ns
SCL “L” pulse width t
SLW 300 ns
Address setup time A0 t
SAS 50 ns
Address hold time t
SAH VSS = –3.0 350 ns
–2.7 400 ns
–2.4 500 ns
Data setup time SI t
SDS 50 ns
Data hold time t
SDH 50 ns
CS-SCL time CS t
CSS 150 ns
t
CSH VSS = –3.0 550 ns
–2.7 650 ns
–2.4 700 ns
[VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C]