Specifications

EPSON 7–13
SED1234/35 Series
SED1234/35
Series
Triple boosting circuit
When a capacitor is connected between CAP1+ and
CAP1-, between CAP2+ and CAP2-, and between V
SS
pin and VOUT pin respectively, the potential between the
V
DD pin and VSS pin is boosted triple and output to the
VOUT pin. In case of double boosting, remove the
capacitor between CAP2+ and CAP2- in connection for
triple boosting operation and strap between CAP2- and
V
OUT pin. Then, a double boosted output can be obtained
from the VOUT pin (CAP2-).
The boosting circuit uses a signal from the oscillator
ourput.
Accordingly, it is necessary that the oscillating circuit
must be in operation. The potential relationship of
boosting is shown below.
Voltage regulating circuit
The voltage regulation circuit regulates the boosted
voltage developed at Vout. It outputs the regulated LCD
driving voltage at the V
5 terminal. An internal resistor
can be inserted into the regulation circuit feedback loop
providing the following voltage levels at the V
5 terminal.
When V
5 is required to be different than the above case,
leave the internal feedback resistor out of the circuit. V
5
can be regulated within a range of |V5|<|VOUT|. It may be
calculated by the following formula:
V
5 = (1+
R
b
) • VREG ································
1
Ra
Wherein, VREG is the constant voltage source inside the
SED1230 Series and the voltage is constant at V
REG
=
3.1V. Voltage regulation of the V5 output is accom-
plished by connecting a variable resistor between V
R,
V
DD and V5. For fine adjustment of the V5 voltage, use
a combination of fixed resistors R1 and R3 and a variable
resistor R2.
The voltage regulator circuit carries a temperature gradi-
ent of about -0.17%/°C under V
REG outputs. When any
other temperature gradient is required, connect a
thermistor in series to the output voltage regulating
register.
Since the V
R terminal has a high input impedance, it is
necessary to take noise suppression measures such as
shortening the input wiring and shielding the wiring run.
Example 1:
Condition: I(R1, R2, R3) ≤ 5µAV5 = –6 to –8V
Setting: R1+R2+R3 = 8V/5µA = 1.6MΩ R1 = 600KΩ
8V = (1+R
b/Ra) 3.0V Rb/Ra = 1.67 ···· R2 = 200KΩ
6V = (1+R
b/Ra) 3.0V Rb/Ra = 1 R3 = 800KΩ
(V
CC
=+3V) V
DD
=0V
(GND) V
SS
=
-3V
V
OUT
=2V
SS
=-6V
Potential during double boosting
R1 R2 R3
V
R
V0
VDD
+
V
5
VREG
-
Ra
Rb
V
DD
=0V
V
SS
=-3V
V
OUT
=3V
SS
=-9V
Potential during triple boosting