Specifications

EPSON 8–11
SED1240 Series
SED1240
Series
System Bus Connecting Pins
Pin name I/O Description Q’ty
D7 (SI) I 8-bit input data bus which is connected to the 16-bit standard MPU 8
D6 (SCL) data bus.
D5 to D0 Pin D7 and pin D6 function as a serial data input and a serial clock
input at P/S = “L”, respectively.
C86: An MPU selecting pin
OPEN: OPEN is allowable, but it is recommend to fix it to one of
potentials as a matter of noise-resistance characteristic.
—: Either “H” or “L” is allowable, but the potential should be fixed.
A0 I Usually used to distinguish data from a command to which the LSB 1
of the MPU address bus is connected.
“L” : Indicates that D0 to D7 are of a command.
“H” : Indicates that D0 to D7 are of data.
RES I Reset pin for initializing the whole IC. Be sure to input it once when 1
the power supply is turned on. A reset operation is performed at the
“L” level of the RES signal.
C86 I MPU selecting pin. Fix it to “H” or “L” depending on the MPU to 1
be used.
“L” : 80 series MPU interface
“H” : 68 series MPU interface
CS I Chip selecting pin. Usually, it inputs a signal that is obtained by 1
decoding an address signal. Chip selection is enabled at the “L”
level.
WR I <When the 80 series MPU is selected> Active “L” 1
(E) A pin for connecting the WR signal of the 80 series MPU.
The signal on the data bus is latched at the rise of the WR signal.
<When the 68 series MPU is connected> Active “H”
Becomes an enable clock input of the 68 series MPU.
P/S I A pin for selecting either serial interface or parallel interface. 1
“L” : Serial interface
“H” : Parallel interface
IF I A data bit length selecting pin at parallel interface. 1
“H” : 8-bit parallel interface
“L” : 4-bit parallel interface
At P/S = “L”, set pins D3 to D0 to V
DD or VSS, or OPEN.
CK I An external clock input pin. 1
When using the internal oscillating circuit, fix it to “H”.
When using an external clock input, the internal oscillating circuit
must be turned off by command.
Pin
P/S C86 I/F D7 D6 D5 D4 D3-D0 CS A0 WR
Mode
Serial I/F “L” H or L — SI SCL OPEN OPEN OPEN CS A0 —
68I/F 8bit “H” “H” “H” D7 D6 D5 D4 D3-D0 CS A0 E
68I/F 4bit “H” “H” “L” D7 D6 D5 D4 OPEN CS A0 E
80I/F 8bit “H” “L” “H” D7 D6 D5 D4 D3-D0 CS A0 WR
80I/F 4bit “H” “L” “L” D7 D6 D5 D4 OPEN CS A0 WR