Specifications

EPSON 8–15
SED1240 Series
SED1240
Series
Boosting circuit
The SED1240 series is provided with a boosting circuit
for triple boosting and double boosting for the potential
between VDD and VSS2.
For triple boosting, connect a capacitor between CAP1+
and CAP1–, between CAP2+ and CAP2–, and between
V
DD and VOUT, and the VDD - VSS2 potential is triple-
boosted to the negative side and output to the V
OUT pin.
For double boosting, connect a capacitor between CAP1+
and CAP1– and between V
DD and VOUT, set CAP2+ to
OPEN, and connect CAP2– to V
OUT, and the VDD - VSS2
potential is double-boosted to the negative side and
output to the VOUT pin.
Because the boosting circuit uses signals from the
oscillator output, the internal oscillating circuit or the
external clock must be in operation.
The relation of boosting voltages is shown below.
Set the potential between the V
DD and VSS2 to ensure that
the VOUT does not exceed the permissible operating
voltage range of V
SS - VOUT (V5) when double or triple
boosted.
V SS2
V OUT
CAP2–
CAP2+
CAP1–
CAP1+
V SS2
V OUT
CAP2–
CAP2+OPEN
CAP1–
CAP1+
V DD = 0V
V
SS2 = –3V
V
OUT = 3V SS2 = –9V
Potential relation of triple boosting voltages
.
.
.
.
V DD = 0V
V
SS2 = –3V
V
OUT = 2V SS2 = –6V
Potential relation of double boosting voltages
.
.
.
.
*Set the V
SS2 voltage range to ensure that VOUT terminal voltage does not exceed the permissible operating
voltage range of VSS - VOUT and absolute maximum rating.