Specifications

EPSON 8–57
SED1240 Series
SED1240
Series
t CSS t CSH
t SAS t SAH
t SLW
t SCYC
t SHW
t SDS t SDH
CS
SCL
A0
SI
Serial Interface
*1: For the rise and fall time of input signals, set 15 ns or less.
*2: Every timing is specified on 20% and 80% of V
SS.
*3: To validate a command or data immediately before the rise of CS,
tCSH must be satisfied at the latch timing of D0
data. If CS is started at another data latch timing, the previous command or data will not be input.
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System clock cycle SCL tSCYC – 700 – ns
SCL “H” pulse width tSHW – 250 – ns
SCL “L” pulse width t
SLW – 250 – ns
Address setup time A0 tSAS –50–ns
Address hold time t
SAH – 250 – ns
Data setup time SI t
SDS –50–ns
Data hold time t
SDH –50–ns
CS-SCL time CS t
CSS – 150 – ns
t
CSH – 500 – ns
[VSS = –5.5 V to –4.5 V, Ta = –30 to 85°C]
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System clock cycle SCL t
SCYC – 1000 – ns
SCL “H” pulse width t
SHW – 300 – ns
SCL “L” pulse width tSLW – 300 – ns
Address setup time A0 t
SAS –50–ns
Address hold time t
SAH – 300 – ns
Data setup time SI t
SDS –50–ns
Data hold time t
SDH –50–ns
CS-SCL time CS t
CSS – 150 – ns
t
CSH – 700 – ns
[VSS = –4.5 V to –2.4 V, Ta = –30 to 85°C]
[VSS = –2.4 V to –1.8 V, Ta = –30 to 85°C]
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System clock cycle SCL t
SCYC – 2000 – ns
SCL “H” pulse width tSHW – 300 – ns
SCL “L” pulse width t
SLW – 300 – ns
Address setup time A0 tSAS –50–ns
Address hold time t
SAH – 500 – ns
Data setup time SI t
SDS –50–ns
Data hold time t
SDH –50–ns
CS-SCL time CS t
CSS – 150 – ns
t
CSH – 900 – ns