Specifications

9–12 EPSON
SED1278
• External segment driver signal timing
LP
0.9 V DD
0.1 V DD
0.1 V DD
0.9 V DD
0.1 V DD
0.9 V DD 0.9 V DD
0.9 V DD
0.1 V DD
0.9 V DD
0.1 V DD
t WCLH
t WCLH
t WCLL
t DSLP
t DHX t OSX
t DFR
t DSLP
0.1 V DD
XSCL
DO
FR
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 75°C)
Parameter Symbol Condition
Rating
Unit
min max
Enable cycle time tcycE 500 — ns
Enable “H” level pulsewidth tWEH 220 — ns
Enable rise/fall time trE, tfE —25ns
RS, R/W setup time tAS 40 — ns
RS, R/W address hold time tAH 10 — ns
Read data setup time tRD CL = 100 pF — 120 ns
Read data hold time tDHR 20 — ns
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 70°C)
Parameter Symbol Condition
Rating
Unit
min max
Clock pulsewidth: High level tWCLH 0.8/2fOSC —ns
Clock pulsewidth: Low level tWCLL 0.8/2fOSC —ns
Latch pulse setup time tDSLP 0.7/2fOSC —ns
Data setup time tOSX 0.7/2fOSC —ns
Data hold time tDHX 0.7/2fOSC —ns
FR delay tDFR –1000 1000 ns