Specifications

9–16 EPSON
SED1278
OPERATION
The Busy Flag
The SED1278 takes between 10 and 410 clock cycles to
execute instructions. During that period additional
instructions should not be issued. The device is provided
with a busy flag to let the user check the internal state of
the chip. BF should be 0 before another instruction is
issued.
If the busy flag is not checked between instructions the
user must arrange for a guaranteed delay of more than the
instruction execution time, before issuing the next
instruction.
4-Bit MPU Interface
If a “System Set” instruction is issued with bit 4 set to 0,
then the SED1278 will operate with a 4-bit MPU data bus
interface.
If a 4-bit interface is used, the 8-bit instructions are
written nibble by nibble; the high-order nibble being
written first, followed by the low-order nibble. It is not
necessary to check the busy flag between writing separate
nibbles of individual instructions.
Reading the Busy Flag/Address Counter yields the high-
order nibble first, followed by the low-order nibble.
System Initialization
Power-on reset
Although the SED1278 has no external reset input, it will
automatically reset on system power-on. The sequence
starts once VDD < 4.5 V.
While the SED1278 is resetting the busy flag is set to 1.
The reset takes about 3,750 clock cycles. For example if
f
OSC = 250 kHz, the reset sequence takes about 30 ms.
Reset places the SED1278 in a state where
• the display is clear.
• the system configuration corresponds to
• IF = 1: 8-bit MPU interface
• N = 0: 1-line display
• F = 0: 1/8 duty cycle
• the display configuration corresponds to
• D = 0: Display off
• C = 0: Cursor off
• B = 0: Blink off
• the entry mode is set to
• I/D = 1: Increment
• S = 1: No display shift