Specifications

EPSON 10–5
SED1280
SED1280
Measurement conditions
The measurement circuit is shown in the following
figure. The switch is in position A until capacitor C
charges to VC volts. It then switches to position B and the
capacitor discharges through the device under test (DUT),
applying a surge voltage to the test pin. All other pins are
left open.
The supply voltages, V
C, increases in 50 V steps from 50
V to a maximum of 1 kV, or until the device breaks down.
Breakdown has occurred if the leakage current between
the test pin and the GND pin increases by 0.1 µA when
the absolute maximum rated voltage is applied to the test
pin.
SW
ABR
C
V
C
GND
Device under
test (DUT)
Signal measurement
pin (other pins open)
AC Electrical Characteristics
Serial data timing
VIH
tWL
tsu tH
tpzv
t
WH
VIL
VIH
VIL
VOH
VOL
SCK
SID
SOD
Expanded segment output timing
VDD = 5 V, VSS = 0 V, Ta = –20 to 75°C
Parameter Symbol Condition
Rating
Unit
min typ max
SCK LOW-level pulsewidth tWL 0.35 – 0.65 µs
SCK HIGH-level pulsewidth tWH 0.35 – 0.65 µs
Data setup time tSU 200 – – ns
Data hold time tH 200 – – ns
Output delay time tPZY – – 200 ns
VDD = 5.0 V, VSS = 0 V, Ta = –20 to 75°C
Parameter Symbol Condition
Rating
Unit
min typ max
LP and XSCL LOW-level pulsewidth tWCLL 0.8×2/fc ––ns
LP and XSCL HIGH-level pulsewidth tWCLH 0.8×2/fc ––ns
XSCL to LP and LP to XSCL setup time tDSLP 0.7×2/fc ––ns
DO to XSCL setup time tOSX 0.7×2/fc ––ns
XSCL to DO hold time tDHX 0.7×2/fc ––ns
FR delay time tDFR –1 – 1 µs