Specifications
10–6 EPSON
SED1280
LP
FR
XSCL
DO
0.9V
DD
0.1V
DD
0.9V
DD
0.1V
DD
0.9V
DD
0.1V
DD
t
WCLH
t
DSLP
t
DSLP
t
WCLH
t
DFR
t
OSX
t
DXH
t
WCLL
Reset timing
V
DD = 5.0 V, VSS = 0 V, Ta = –20 to 75°C
V
DD
RST
4.5 V
4.5 V
0.2 V
0.2 V
t
r
t
RST
t
f
Note: 0.1 ms ≤ tr ≤ 10 ms, tf ≥ 1 ms, tRST ≥ 30 ms.
FUNCTIONAL DESCRIPTION
Serial Data Communication
The SED1280 uses a synchronous serial data system,
with all timing referenced to SCK. Data communication
uses a 4-bit synchronization pattern.
Serial data reception
Data input on SID is clocked into the receiver buffer on
the falling edge of SCK as shown in the following figure.
001
Sync character
SCK
SID
Register
address
Data
Block data
0 RA0 RA1 RA2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
As the buffer state is undefined after power-ON, RST
should be momentarily held LOW after power-ON to set
all bits of the buffer to 1.
Data loaded into the buffer is compared with the
synchronization pattern. If a match is detected, the next
bit is treated as the start of the data block. The
synchronization pattern should be repeated between
consecutive blocks as shown in the following figure.
Sync character Sync characterBlock data
Block
data
RA0
SCK
SID
DB7 RA0 DB7
Data reception limits
The receiver incorporates two data buffers—buffer 1 and
buffer 2. When continuously receiving data, buffer 1 fills
first, then buffer 2. New data blocks are only received
when both buffers are empty. New data is lost if it is sent
while the controller is processing data in one or both
buffers. The busy status bit, ST1, is set to 1 while the
controller is processing data.
Note that new data cannot be recieved while data is being
transmitted, and that two data blocks received
consecutively are treated as a single block.