Specifications

EPSON 10–7
SED1280
SED1280
Serial data transmission
SWC1 to SWC10 and EI1 to EI3 are scanned and their
input logic levels transmitted serially from SOD as
shown in the following figure. Data is clocked out on the
falling edge of SCK.
As the state of SOD is undefined after power-ON, RST
should be momentarily held LOW after pow-ON to set
SOD HIGH. SOD remains HIGH until the first command
from the host is received and returns HIGH when data
transmission is complete.
Data transmission and reception timing
Data transmission starts from the first falling edge of
SCK after a block of data has been received. If two
blocks of data are received consecutively, data
transmission starts from the first falling edge of SCK
after the first block has been received, as shown in the
following figure.
Status bit
The ST1 status bit indicates that the controller is processing
received data and cannot receive new data. When ST1 is
HIGH, data is being processed and the host should not
transmit new data until ST1 is LOW.
The host shoulld begin checking ST1, as shown in the
following figure, as soon as it transmits new data.
Input port
data
Key input data
Status bit
Key register
address
SWC10
DB9DB 8DB7DB6DB5DB4DB3DB 2DB1DB0KB2KB1KB0SB2SB1SB0ST
SWC9
to
SWC1
Sync
character
SCK
SOD
Transmission start
SCK
SID
SOD