Specifications

10–10 EPSON
SED1280
Data transmission flow charts
The following figures show the 1278 core display data
RAM processing when data is transferred from the host
to the SED1280.
Transmission using the busy bit
Start
Register address
0 1 Address data
DDRAM write data
1
2
XXXXXXXX
DB7 to DB0
Finished receiving?
Finished receiving?
End
Dummy command
NO
1
0
1
0
YES
NO
YES
Busy bit?
Busy bit?
1278 instruction register
1278 data register
Data
transmission
check
Data
Check if
receiving
Data
Data
transmission
check
Check if
receiving
Confirmation that
processing is
finished
Timed access transmission
1
Address data
DDRAM write data
Initialization
complete
Register address
0
1
DB7 DB0to
5 ms
5 ms
5 ms
Initialization
complete
1278 instruction register
1278 data register