Specifications

10–14 EPSON
SED1280
LED controller timing
The LED controller timing for one scan and a series of
scans is shown in the following figures.
SWS1
SWS2
SWS3
SWS8
LE1
LE2
LE1
RST
1.0 ms
LED control period
Key scan period
0.9 ms
1.0 ms 1.0 ms
0.9 ms
0.9 ms
LE2
LE5
LE5
5 ms 5 ms
40 ms
.
.
.
.
.
.
LED controller limits
Up to 25 mA can be drawn from any one of SWS1 to
SWS8 with a maximum total of 100 mA for all eight pins.
As the SED1280 does not current limit its outputs, the
host should limit the number of LEDs that are ON
simultaneously. For example, if a LED draws 5 mA, a
maximum of 20 LEDs can be ON simultaneously.
DESIGN INFORMATION
Although the SED1280 contains an SED1278 core, there
are some important differences. The following points
should be noted when designing a system using an
SED1280.
System Clock
The 1 MHz SED1280 system clock is divided by four to
generate the 250 kHz clock used by the SED1278 core.
Accordingly, the SED1278 requires four times as many
clock cycles as the SED1280 to execute the same
instruction. The system clock must be connected, even
if data transfer or key scanning is not used.
Data Interface
The SED1280 core data interface is eight bits wide. The
SED1278 interface width is set to eight by setting the IF
bit in the System Set instruction to 1.
Data Output
The SED1280 does not support the SED1278 function
allowing the host to read the DDRAM and CGRAM
address counter. The SED1280 does, however, provide
the ST1 busy bit output, which can be read by the host.