Integration Instructions

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FSS JODY-W263 Integration Instructions Rev 02.docx
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• For PCBs using components larger than 0402 and dielectric thickness below 200
µm, it is recommended to add a keep-out (that is, clearance, a void area) on the
ground reference layer below any pin present on the RF transmission lines to
reduce parasitic capacitance to ground.
• The transmission lines width and spacing to GND must be uniform and routed as
smoothly as possible: route RF lines in 45° angle.
• Add GND stitching vias around transmission lines as shown in Figure 2.
• Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to
main ground layer, providing enough vias on the adjacent metal layer as shown
in Figure 2.
• Route RF transmission lines far from any noise source (as switching supplies and
digital lines) and from any sensitive circuit to avoid crosstalk between RF traces
and Hi-impedance or analog signals.
• Avoid stubs on the transmission lines, any component on the transmission line
should be placed with the connected pin over the trace. Also avoid any
unnecessary component on RF traces.
Figure 2: Example of RF trace and ground design from JODY-W2 EVK