Integration Instructions

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FSS JODY-W263 Integration Instructions Rev 02.docx
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4.3 Other remarks
4.3.1 Unused pins
☞ JODY-W2 modules have pins that are reserved for future use (NC). These pins must be left
unconnected on the application board.
4.3.2 GPIO usage
☞ The reconfiguration of signals marked as GPIOs on the JODY-W2 module for applications not
listed in this document depends on the respective firmware release.
5 Design-in
5.1 Overview
For an optimal integration of JODY-W2 series modules in the final application board, it is
advisable to follow the design guidelines described in this chapter. Every application circuit must
be properly designed to ensure that the related interface functions correctly, but several specific
points require special attention during the design of the application device.
The following list provides a rank of importance in the application design, starting from the
highest relevance:
• Module antenna connection: ANT0 and ANT1 pins.
Antenna circuit affects the RF compliance of the device integrating JODY-W2
modules with applicable certification schemes. For schematic and layout design
recommendations, see also Antenna interfaces.
• Module supply: VBAT, VIO/1V8, and GND pins.
The supply circuit affects the RF compliance of the device integrating JODY-W2 modules
with applicable certification schemes. Follow the General high-speed layout guidelines.
• High speed interfaces: SDIO pins.
High speed interfaces can be a source of radiated noise and can affect the compliance
with regulatory standards for radiated emissions. Follow the General high-speed layout
guidelines and recommendations for the SDIO 3.0 interface.
• System functions: PDn and pins described as Configuration pins.
Accurate design is required to ensure that the voltage level is well defined during
module boot. Follow the General high-speed layout guidelines.
• Other pins: High speed UART, PCM, specific signals and NC pins.