Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC860T (Rev. D) Fast Ethernet Controller Supplement to the MPC860 PowerQUICC™ User’s Manual MPC860TAD/D Rev. 0.8, 09/1999 ª PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. DigitalDNA and Mfax are trademarks of Motorola, Inc. Freescale Semiconductor, Inc... The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors This document contains information on a new product under development.
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Chapter 1 Freescale Semiconductor, Inc... Overview 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.5 Document Revision History................................................................................. 1-1 Overview.............................................................................................................. 1-1 Comparison with the MPC860.............................................................................
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Chapter 4 Parallel I/O Ports 4.1 4.1.1 4.1.2 Port D Pin Functions.............................................................................................4-1 Port D Registers................................................................................................4-2 Enabling MII Mode ..........................................................................................4-2 Chapter 5 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. CONTENTS Paragraph Number 6.3.1 6.3.2 6.3.2.1 6.3.2.2 6.4 6.4.1 6.4.2 Title Page Number Hardware Initialization...................................................................................6-22 User Initialization (before Setting ECNTRL[ETHER_EN]) .........................6-22 Descriptor Controller Initialization ............................................................6-23 User Initialization (after Asserting ECNTRL[ETHER_EN]) ....................
Freescale Semiconductor, Inc. CONTENTS Title Page Number Freescale Semiconductor, Inc... Paragraph Number vi MPC860T (Rev. D) Fast Ethernet Controller Supplement PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 1-1 1-2 1-3 3-1 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 7-1 7-2 7-3 7-4 7-5 MOTOROLA Title Page Number MPC860T Block Diagram .................................................................................. 1-4 MPC860T Interrupt Structure .............................................................................
Freescale Semiconductor, Inc. ILLUSTRATIONS Title Page Number Freescale Semiconductor, Inc... Figure Number viii MPC860T (Rev. D) Fast Ethernet Controller Supplement PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 1-1 2-1 3-1 3-2 3-3 3-4 4-1 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-27 MOTOROLA Title Page Number Document Revision History................................................................................ 1-1 FEC Signal Descriptions.....................................................................................
Freescale Semiconductor, Inc. TABLES Table Number Page Number Receive Buffer Descriptor (RxBD) Field Description...................................... 6-25 Transmit Buffer Descriptor (TxBD) Field Descriptions................................... 6-26 MII Receive Signal Timing ................................................................................ 7-2 MII Transmit Signal Timing............................................................................... 7-2 MII Async Inputs Signal Timing ........
Freescale Semiconductor, Inc. Chapter 1 Overview Freescale Semiconductor, Inc... 10 10 This chapter provides an overview of Rev. D of the MPC860T, focussing primarily on the Fast Ethernet controller (FEC). It provides a discussion of its basic features and a general look at how the MPC860T can be implemented. This document is provided as a supplement to the MPC860 PowerQUICC UserÕs Manual.
Freescale Semiconductor, Inc. The MPC860T integrates three separate processing blocks. The Þrst two, common with all MPC860 devices, are as follows: ¥ A high-performance PowerPCª core that can be used as a general purpose processor for application programming ¥ A RISC engine embedded in the communications processor module (CPM) designed to provide the communications protocol processing provided by the MPC860MH. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. ¥ management of transmit and receive buffer memory 10/100 base-T media access control (MAC) features Ñ Address recognition for broadcast, single station address, promiscuous mode, and multicast hashing Ñ Full support of media-independent interface (MII) Ñ Interrupts supported per frame or per buffer (selectable buffer interrupt functionality using the I bit is not supported however.) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Instruction Bus Embedded PowerPC Processor Core 4-KByte Instruction Cache System Interface Unit (SIU) Unified Bus Memory Controller Instruction MMU Load/Store Bus Internal External Bus Interface Bus Interface Unit Unit 4-KByte Data Cache System Functions Data MMU Real-Time Clock Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. in memory management of transmit and receive data frames. External memory (DRAM) is inexpensive, and because BD rings in external memory have no inherent size limitations, memory management easily can be optimized to system needs. 1.4.2 SIU Interrupt ConÞguration As shown in Figure 1-2, the SIU receives interrupts from internal sources, such as the FEC and other modules and external pins, IRQ[0Ð7]. System Interface Unit SWT NMI GEN Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Figure 1-3 shows the glueless connection of the serial channels to physical layer framers and transceivers. MPC8xx 100Base-T Transceiver Freescale Semiconductor, Inc... 10Base-T Transceiver MII FEC “7-wire” interface SCC1 (Ethernet) SCC2 (QMC) T1 Framer TDM SCC3 (QMC) RS-232 Transceiver SCC4 (UART) Figure 1-3. MPC860T Serial Configuration 1-6 MPC860T (Rev.
Freescale Semiconductor, Inc. Chapter 2 FEC External Signals 20 20 Freescale Semiconductor, Inc... This chapter contains brief descriptions of the MPC860T FEC input and output signals in their functional groups. 2.1 Signal Descriptions The MPC860T system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how the user assigns them.
Freescale Semiconductor, Inc. Table 2-1. FEC Signal Descriptions (Continued) Name PD[12] L1RSYNCB MII_MDC Pin Number R16 Description General-purpose I/O port D bit 12ÑThis is bit 12 of the general-purpose I/O port D. L1RSYNCBÑInput receive data sync signal to the TDM channel B. MII management data clockÑOutput clock provides a timing reference to the PHY for data transfers on the MDIO signal. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 2-1. FEC Signal Descriptions (Continued) Name PD[4] REJECT3 MII_TXD[2] Pin Number U16 Description General-purpose I/O port D bit 4ÑThis is bit 4 of the general-purpose I/O port D. Reject 3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. MII transmit data 2ÑOutput signal TXD[2] represents bit 2 of the nibble of data when TX_EN is asserted and has no meaning when TX_EN is negated.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 2-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.
Freescale Semiconductor, Inc. Chapter 3 Fast Ethernet Controller Operation 30 30 Freescale Semiconductor, Inc... This chapter discusses the operation of the FEC. 3.1 Transceiver Connection The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10-Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE], described in Section 6.2.20, ÒReceive Control Register (R_CNTRL).Ó Table 3-1 shows the 18 MII interface signals that are deÞned by the 802.
Freescale Semiconductor, Inc. Table 3-2. Serial Mode Connections to the External Transceiver Freescale Semiconductor, Inc... Signal Description FEC Signal Name Transmit clock TX_CLK Transmit enable TX_EN Transmit data TXD0 Collision COL Receive clock RX_CLK Receive enable RX_DV Receive Data RXD0 Unused 860T inputsÑTie to ground RX_ER, CRS, RXD[3:1] Unused 860T outputsÑIgnore TX_ER, TXD[3:1], MDC, MDIO 3.2 FEC Frame Transmission FEC transmissions require almost no host intervention.
Freescale Semiconductor, Inc. (I_EVENT[BABT] = 1); however, the entire frame is sent (no truncation). Whether buffer or frame interrupts can be generated is determined by I_MASK settings. To pause transmission, set the graceful transmit stop bit, X_CNTRL[GTS]. When GTS is set, the FEC transmitter stops immediately if no transmission is in progress or continues transmission until the current frame either Þnishes or terminates with a collision.
Freescale Semiconductor, Inc. of the frame to the associated data buffer. R_BUFF_SIZE[R_BUFF_SIZE] determines buffer length, which should be at least 128 bytes. R_BUFF_SIZE must be quad-word (16-byte) aligned. During reception, the FEC checks for a frame that is either too short or too long. When the frame ends (CRS is negated), the receive CRC Þeld is checked and written to the data buffer. The data length written to the last BD in the Ethernet frame is the length of the entire frame.
Freescale Semiconductor, Inc. broadcast address. If it is, the frame is accepted unconditionally; otherwise (multicast address) a hash table lookup is performed using the 64-entry hash table deÞned in the hash table registers. In promiscuous mode (R_CNTRL[PROM] = 1), the FEC receives all the incoming frames regardless of their address. In this mode the DA lookup is still performed and the MISS bit in the RxBD is set accordingly.
Freescale Semiconductor, Inc. of the CRC-encoded result to generate a number between 0 and 63. Bit 31 of the CRC result selects HASH_TABLE_HIGH (bit 31 = 1) or HASH_TABLE_LOW (bit 31 = 0). Bits 30Ð26 of the CRC result select the bit in the selected register. If that bit is set in the hash table, the frame is accepted; otherwise, it is rejected. The result is that if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.
Freescale Semiconductor, Inc. 3.10 Internal and External Loopback The FEC supports Both internal and external loopback. In loopback mode, both FIFOs are used and the FEC operates in full-duplex fashion. Both internal and external loopback are conÞgured through R_CNTRL[LOOP, DRT]. For internal loopback, set LOOP = 1 and DRT = 0. TX_EN and TX_ER are not asserted during internal loopback. For external loopback, set LOOP = 0 and DRT = 0. ConÞgure the external transceiver for loopback.
Freescale Semiconductor, Inc. Table 3-4. Reception Errors Error Description Overrun Error The FEC maintains an internal FIFO for receiving data. If a receiver FIFO overrun occurs, the FEC closes the buffer and sets RxBD[OV]. Non-Octet The FEC handles up to seven dribbling bits when the receive frame terminates nonoctet aligned and Error it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the frame nonoctet (Dribbling Bits) aligned (NO) error is reported in the RxBD.
Freescale Semiconductor, Inc. Chapter 4 Parallel I/O Ports 40 40 Freescale Semiconductor, Inc... This chapter shows how to use port D pin multiplexing to support Fast Ethernet controller (FEC) operations. 4.1 Port D Pin Functions Each of the 13 port D pins is independently conÞgured as a general-purpose I/O pin if the corresponding port D pin assignment register (PDPAR) bit is cleared. Each pin is conÞgured as a dedicated on-chip peripheral pin if the corresponding PDPAR bit is set.
Freescale Semiconductor, Inc. Table 4-1 shows the port D pin assignments. Table 4-1. Port D Pin Assignment Signal Function Signal PDPAR=1 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Chapter 5 SDMA Bus Arbitration and Transfers Freescale Semiconductor, Inc... 50 50 This chapter describes SDMA functions speciÞc to the MPC860T, particularly where the functionality differs from the MPC860. For a full discussion of SDMA bus arbitration and transfers, refer to the MPC860 PowerQUICC UserÕs Manual. 5.1 Overview The MPC860T has two arbitration levels to considerÑaccesses to the SDMA hardware and accesses to the 60x bus.
Freescale Semiconductor, Inc. 5.2.1 SDMA ConÞguration Register (SDCR) The SDMA conÞguration register (SDCR), shown in Figure 5-2, is used to conÞgure all 16 SDMA channels. It is always read/write in supervisor mode, although writing to the SDCR is not recommended unless the CPM is disabled. SDCR interacts with the DMA controllers in the FEC. Refer to the MPC860 PowerQUICC UserÕs Manual for more information. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Chapter 6 Programming Model 60 60 Freescale Semiconductor, Inc... This chapter gives an overview of the MPC860T implementation of the Fast Ethernet controller (FEC) registers, buffer descriptors (BDs), and initialization. 6.1 Overview The FEC software model is similar to that used by the 10-Mbps Ethernet implemented on the MPC860 core device. To support higher data rates, the FEC has a different internal architecture, which changes the programming model slightly.
Freescale Semiconductor, Inc. Table 6-1. FEC Parameter RAM Memory Map (Continued) Freescale Semiconductor, Inc... Address Name Description Section 0xE40 ECNTRL Ethernet control register 6.2.8 0xE44 IEVENT Interrupt event register 6.2.9 0xE48 IMASK Interrupt mask register 6.2.9 0xE4C IVEC Interrupt level and vector status 6.2.10 0xE50 R_DES_ACTIVE Receive ring updated ßag 6.2.11 0xE54 X_DES_ACTIVE Transmit ring updated ßag 6.2.12 0xE80 MII_DATA MII data register 6.2.
Freescale Semiconductor, Inc. Table 6-2 describes the ADDR_LOW Þelds. Table 6-2. ADDR_LOW Field Descriptions Bits Name Description 0Ð31 ADDR_LOW Bytes in the 6-byte address: 0 (bits 0Ð7), 1 (bits 8Ð15), 2 (bits 16Ð23) and 3 (bits 24Ð31) 6.2.2 RAM Perfect Match Address High (ADDR_HIGH) Freescale Semiconductor, Inc... The ADDR_HIGH register, shown in Figure 6-2, is written by and must be initialized by the user.
Freescale Semiconductor, Inc. Bits 1 2 3 4 5 6 7 8 Field HASH_HIGH Reset UndeÞned R/W Read/write Addr 0xE08 Bits Freescale Semiconductor, Inc... 0 16 17 18 19 20 21 22 23 24 Field HASH_HIGH Reset UndeÞned R/W Read/write Addr 0xE0A 9 10 11 12 13 14 15 25 26 27 28 29 30 31 Figure 6-3. HASH_TABLE_HIGH Register Table 6-4 describes HASH_TABLE_HIGH Þelds. Table 6-4.
Freescale Semiconductor, Inc. Table 6-5 describes HASH_TABLE_LOW Þelds. Table 6-5. HASH_TABLE_LOW Field Descriptions Bits Name 0Ð31 Description HASH_LOW Contains the lower 32 bits of the 64-bit hash table used in address recognition for receive frames with a multicast address. HASH_LOW[0] contains hash index bit 31. HASH_LOW[31] contains hash index bit 0. Freescale Semiconductor, Inc... 6.2.
Freescale Semiconductor, Inc. Bits 0 1 2 3 5 6 7 8 Field X_DES_START Reset UndeÞned R/W Read/write Addr 0xE14 Bits 16 17 18 19 Field Freescale Semiconductor, Inc... 4 20 21 22 23 24 9 10 11 12 13 14 15 25 26 27 28 29 30 31 X_DES_START 00 Reset UndeÞned R/W Read/write Addr 0xE16 Figure 6-6. X_DES_START Register Table 6-7 describes X_DES_START Þelds. Table 6-7.
Freescale Semiconductor, Inc. Bits 0 1 2 4 5 6 7 8 Field Ñ Reset UndeÞned R/W Read/write Addr 0xE18 Bits 16 17 18 Field Freescale Semiconductor, Inc... 3 19 20 21 22 23 Ñ 24 9 10 11 12 13 14 15 25 26 27 28 29 30 31 R_BUFF_SIZE Reset UndeÞned R/W Read/write Addr 0xE1A Ñ Figure 6-7. R_BUFF_SIZE Register Table 6-8 describes R_BUFF_SIZE Þelds. Table 6-8. R_BUFF_SIZE Field Descriptions Bits Name Description 0Ð20 Ñ 21Ð27 R_BUFF_SIZE 28Ð31 Ñ Reserved.
Freescale Semiconductor, Inc. Table 6-9 describes ECNTRL Þelds. Table 6-9. ECNTRL Field Descriptions Bits Name 0Ð7 Ñ Reserved. These Þelds may return unpredictable values and should be masked on a read. Users should always write these Þelds to zero. 8Ð28 Ñ These Þelds may return unpredictable values and should be masked on a read. Users should always write these Þelds to zero. Freescale Semiconductor, Inc... 29 Description FEC_PINMUX FEC enable. Read/write.
Freescale Semiconductor, Inc. and RFINT to notify at the end of frame. Table 6-10. I_EVENT/I_MASK Field Descriptions Bits Freescale Semiconductor, Inc... 0 Name Description HBERR Heartbeat error. When I_EVENT[HBC] is set, this interrupt indicates that heartbeat was not detected within the heartbeat window following a transmission. 1 BABR Babbling receive error. Indicates a received frame exceeded MAX_FRAME_LENGTH bytes.
Freescale Semiconductor, Inc. Bits 0 1 Field 2 3 4 5 6 8 ILEVEL 9 0000_0000_0000_0000 R/W Read/write Addr 0xE4C 16 17 10 11 12 13 14 15 26 27 28 29 30 31 Ñ Reset Bits 18 19 20 Field 21 22 23 24 25 Ñ Reset IVEC Ñ Read only Ñ 0000_0000_0000_0000 R/W Ñ Addr Freescale Semiconductor, Inc... 7 0xE4E Figure 6-10. IVEC Register Table 6-11 describes IVEC Þelds. Table 6-11. IVEC Field Descriptions Bits 0Ð2 Name Description ILEVEL Interrupt level.
Freescale Semiconductor, Inc. Bits 0 1 2 Freescale Semiconductor, Inc... Field 3 4 5 6 Ñ 7 8 9 10 11 R_DES_ACTIVE 12 13 14 15 Ñ Reset 0000_0000_0000_0000 R/W Read/write Addr 0xE50 Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0000_0000_0000_0000 R/W Read/write Addr 0xE52 Figure 6-11. R_DES_ACTIVE Register Table 6-12 describes R_DES_ACTIVE Þelds. Table 6-12.
Freescale Semiconductor, Inc. Bits 0 1 2 Field 4 5 6 Ñ 7 8 R/W Read/write Addr 0xE54 17 18 19 10 11 20 21 22 23 12 13 14 15 28 29 30 31 Ñ 0000_0000_0000_0000 16 9 X_DES_ACTIVE Reset Bits Freescale Semiconductor, Inc... 3 24 Field Ñ Reset 0000_0000_0000_0000 R/W Read/write Addr 0xE56 25 26 27 Figure 6-12. X_DES_ACTIVE Register Table 6-13 describes X_DES_ACTIVE Þelds. Table 6-13.
Freescale Semiconductor, Inc. Bits 0 Field 2 ST 3 4 5 OP 6 7 8 R/W Read/write Addr 0xE80 17 18 10 19 20 21 22 11 12 13 14 RA UndeÞned 16 9 PA Reset Bits Freescale Semiconductor, Inc... 1 23 24 Field DATA Reset UndeÞned R/W Read/write Addr 0xE82 25 26 27 15 TA 28 29 30 31 Figure 6-13. MII_DATA Register Table 6-14 describes MII_DATA Þelds. Table 6-14. MII_DATA Field Descriptions Bits Name Description 0Ð1 ST Start of frame delimiter.
Freescale Semiconductor, Inc. completes. At this time the contents of MII_DATA match the original value written except for the DATA Þeld, whose contents have been replaced by the value read from the PHY register. Writing to MII_DATA during frame generation alters the frame contents. Software should use the MII_DATAIO_COMPL interrupt to avoid writing to the MII_DATA register during frame generation. 6.2.14 MII Speed Control Register (MII_SPEED) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. be non-zero to source a read or write management frame. After the management frame is complete, MII_SPEED may optionally cleared to turn off the MDC. The MDC generated has a 50% duty cycle except when MII_SPEED is changed during operation (changes take effect following either a rising or falling edge of MDC). If the system clock is 25 MHz, programming this register to 0x0000_000A generates an MDC frequency of 25 MHz * 1/10 = 2.5 MHz.
Freescale Semiconductor, Inc. Table 6-17. R_BOUND Field Descriptions Bits Name 22Ð29 R_BOUND 30Ð31 Ñ Description Read-only. Highest valid FIFO RAM address. Reserved. Should be written to zero by the host processor. 6.2.16 FIFO Receive Start Register (R_FSTART) Freescale Semiconductor, Inc... The R_FSTART register, shown in Figure 6-16, is programmed by the user to indicate the starting address of the receive FIFO. R_FSTART marks the boundary between the transmit and receive FIFOs.
Freescale Semiconductor, Inc. for the system bus. Setting the watermark to a high value lowers the risk of a transmit FIFO underrun due to system bus contention. Bits 0 2 3 4 5 6 7 8 9 Field Ñ Reset 0000_0000_0000_0000 R/W Read/write Addr 0xED0 Bits 16 Field Freescale Semiconductor, Inc... 1 17 18 19 20 21 22 23 24 25 10 11 12 13 14 15 26 27 28 29 30 31 Ñ X_WMRK Reset 0000_0000_0000_0000 R/W Read/write Addr 0xEDC Figure 6-17.
Freescale Semiconductor, Inc. Bits 0 2 3 4 5 6 7 8 9 Field Ñ Reset 0000_0000_0000_0000 R/W Read/write Addr 0xEEC Bits Freescale Semiconductor, Inc... 1 16 17 18 19 20 21 22 23 24 25 10 11 12 13 14 15 26 27 28 29 30 31 Field Ñ 1 X_FSTART Ñ Reset 0000_0 1 Microcode dependent 00 R/W Read/write Addr 0xEEE Figure 6-18. X_FSTART Register Table 6-20 describes X_FSTART Þelds. Table 6-20. X_FSTART Field Descriptions Bits Name Description 0Ð21 Ñ Reserved.
Freescale Semiconductor, Inc. Table 6-21 describes FUN_CODE Þelds. Freescale Semiconductor, Inc... Table 6-21. FUN_CODE Field Descriptions Bits Name Description 0 Ñ 1Ð2 DATA_BO 3Ð4 DESC_BO The byte order Þeld supplied to the SDMA interface during receive and transmit open descriptor DMA transfers, and during close descriptor DMA transfers. 00 Reserved 01 PowerPC little-endian byte ordering.
Freescale Semiconductor, Inc. Table 6-22 describes R_CNTRL Þelds. Table 6-22. R_CNTRL Field Descriptions Bits Name 0Ð26 Ñ 27 BC_REJ 28 PROM Freescale Semiconductor, Inc... 29 Description Reserved. This bit reads as zero. Broadcast frame reject. If set, frames with DA + 0xFFFF_FFFF_FFFF are rejected unless the PROM bit set. If both BC_REJ and PROM = 1, frames with broadcast DA are accepted and RxBD[M] is set. Promiscuous mode. 0Promiscuous mode disabled 1Promiscuous mode enabled.
Freescale Semiconductor, Inc. Table 6-22 describes R_HASH Þelds. Table 6-23. R_HASH Field Descriptions Bits Name 0Ð7 Ñ Reserved for internal use. When read, these bits are unpredictable. 8Ð20 Ñ Reserved. These bits are read as zeros. Freescale Semiconductor, Inc... 21Ð31 Description MAX_FRAME_LENGTH User read/write Þeld. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FRAME_LENGTH cause an BABT interrupt.
Freescale Semiconductor, Inc. Table 6-24. X_CNTRL Field Descriptions Bits Name Description 31 GTS Graceful transmit stop. When GTS is set, the MAC stops transmission after any frame being transmitted is complete and INTR_EVENT[GRA] is set. If frame transmission is not underway, the GRA interrupt is asserted immediately. When transmission completes, clearing GTS causes the next frame in the transmit FIFO to be sent.
Freescale Semiconductor, Inc. exact values depend on the application. The sequence resembles that shown in Table 6-27. Table 6-27. User Initialization (before Setting ECNTRL[ETHER_EN]) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. (though these steps could also be done before setting ETHER_EN). Table 6-27. User Initialization (after Setting ECNTRL[ETHER_EN]) Step Description 1 Fill RxBD ring with empty buffers 2 Set R_DES_ACTIVE Freescale Semiconductor, Inc... 6.4 Buffer Descriptors (BDs) Data for Fast Ethernet frames must reside in memory external to the MPC860T device.
Freescale Semiconductor, Inc. +0 +2 +4 +6 0 E 1 RO1 2 W 3 RO2 4 L 5 0 6 0 7 8 9 10 M BC MC LG DATA LENGTH RX BUFFER POINTER A[0Ð15] RX BUFFER POINTER A[16Ð31] 11 NO 12 SH 13 CR 14 OV 15 TR Figure 6-23. Receive Buffer Descriptor (RxBD) The RxBD format is shown in Table 6-27. Freescale Semiconductor, Inc... Table 6-27. Receive Buffer Descriptor (RxBD) Field Description Bits Name Description 0 E Empty. Written by the FEC and user.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 6-27. Receive Buffer Descriptor (RxBD) Field Description (Continued) Bits Name Description 14 OV Overrun, written by FEC. A receive FIFO overrun occurred during frame reception. If OV = 1, the other status bits, M, LG, NO, SH, CR, and CL lose their normal meaning and are cleared. This bit is valid only if the L bit is set. 15 TR Truncate. Set if the receive frame is truncated (³ 2 Kbytes).
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued) Bits Name Description 2 W 3 TO2 4 L 5 TC 6 DEF Defer indication, written by FEC (valid if L = 1). Set when the FEC had to defer while trying to transmit a frame. This bit is not set if a collision occurs during transmission. 7 HB Heartbeat error, written by FEC (valid if L = 1).
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 6-28 MPC860T (Rev. D) Fast Ethernet Controller Supplement For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.
Freescale Semiconductor, Inc. Chapter 7 Electrical Characteristics Freescale Semiconductor, Inc... 70 10 This chapter contains detailed information on DC and AC electrical characteristics and AC timing speciÞcations for the MPC860T MII signals and a MPC860T pinout diagram. For information on maximum ratings, thermal characteristics, power considerations, and layout practices, see the MPC860 PowerQUICC Hardware SpeciÞcations. Note: These preliminary speciÞcations are based on design simulations.
Freescale Semiconductor, Inc. M3 RX_CLK (input) M4 RXD[3:0] (inputs) RX_DV RX_ER M1 M2 Freescale Semiconductor, Inc... Figure 7-1. MII Receive Signal Timing Diagram The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the RX_CLK frequency - 1%. Table 7-1.
Freescale Semiconductor, Inc. M7 TX_CLK (input) M5 M8 TXD[3:0] (outputs) TX_EN TX_ER Freescale Semiconductor, Inc... M6 Figure 7-2. MII Transmit Signal Timing Diagram 7.3.3 MII Async Inputs Signal Timing (CRS, COL) Table 7-3 provides information on the MII async inputs signal timing, shown in Figure 7-3. Table 7-3. MII Async Inputs Signal Timing Num M9 Characteristic Min CRS, COL minimum pulse width 1.5 Max Ñ Unit TX_CLK period Figure 7-3 shows the MII asynchronous inputs signal timing diagram.
Freescale Semiconductor, Inc. 7.3.4 MII Serial Management Channel Timing (MDIO,MDC) Table 7-4 provides information on the MII serial management channel signal timing, shown in Figure 7-4. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 7-4. MII Serial Management Channel Timing Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 7.4 MPC860T Pin Assignments Figure 7-5 shows the MPC860T pin assignments. Pins that support the FEC are shown in black.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 7-6 MPC860T (Rev. D) Fast Ethernet Controller Supplement For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA Chapter 7. Electrical Characteristics For More Information On This Product, PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.