Dual-Core Intel® Xeon® Processor 5000 Series Datasheet May 2006 Document Number: 313079-001
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Contents 1 Introduction................................................................................................................. 9 1.1 Terminology ..................................................................................................... 11 1.2 State of Data .................................................................................................... 12 1.3 References .......................................................................................................
6.2.6 6.2.7 Tcontrol and Fan Speed Reduction ............................................................79 Thermal Diode........................................................................................79 7 Features ....................................................................................................................83 7.1 Power-On Configuration Options ..........................................................................83 7.2 Clock Control and Low Power States ................
8-1 Boxed Dual-Core Intel Xeon Processor 5000 Series 1U Passive/2U Active Combination Heat Sink (With Removable Fan) ............................. 89 8-2 Boxed Dual-Core Intel Xeon Processor 5000 Series 2U Passive Heat Sink .................. 90 8-3 2U Passive Dual-Core Intel Xeon Processor 5000 Series Thermal Solution (Exploded View) ....................................................................... 90 8-4 Top Side Board Keep-Out Zones (Part 1) ........................................................
7-1 8-1 8-2 8-3 6 Power-On Configuration Option Lands...................................................................83 PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................ 100 Fan Specifications for 4-pin Active CEK Thermal Solution....................................... 100 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution........................
Revision History Revision 001 Description Initial release Dual-Core Intel® Xeon® Processor 5000 Series Datasheet Date May 2006 7
Features Dual-Core processor Available at 3.
Introduction 1 Introduction The Dual-Core Intel® Xeon® Processor 5000 series are Intel dual core products for dual processor (DP) servers and workstations. The Dual-Core Intel Xeon Processor 5000 series are 64-bit server/workstation processors utilizing two physical Intel NetBurst® microarchitecture cores in one package. The Dual-Core Intel Xeon Processor 5000 series include enhancements to the Intel NetBurst microarchitecture while maintaining the tradition of compatibility with IA-32 software.
Introduction and can thus help improve the overall security of the system. For further information on Execute Disable Bit functionality see http://www.intel.com/cd/ids/developer/asmo-na/ eng/149308.htm. The Dual-Core Intel Xeon Processor 5000 series support Intel® Virtualization Technology, virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction • Thermal Design Power – Processor thermal solutions should be designed to meet this target. It is the highest expected sustainable power while running known power intensive real applications. TDP is not the maximum power that the processor can dissipate. • LGA771 socket – The Dual-Core Intel Xeon Processor 5000 series interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket.
Introduction Document Dual-Core Intel ® Xeon ® Intel Order Number Processor 5000 Series Specifications Update 313065 EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI) Specification for Entry Chassis Power Supplies http:// www.ssiforum.org Entry-Level Electronics-Bay Specifications: A Server System Infrastructure (SSI) Specification for Entry Pedestal Servers and Workstations http:// www.ssiforum.
Introduction 14 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel Xeon Processor 5000 series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Dual-Core Intel Xeon Processor 5000 series are capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Electrical Specifications The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the IA32_FLEX_BRVID_SEL MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3A &3B.
Electrical Specifications 2.4.2 Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the DualCore Intel Xeon Processor 5000 series. Since these PLLs are analog in nature, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (that is, maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT.
Electrical Specifications 2.5 Voltage Identification (VID) The Voltage Identification (VID) specification for the Dual-Core Intel Xeon Processor 5000 series set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to VTT. Please refer to Table 2-12 for the DC specifications for these signals. A minimum voltage is provided in Table 2-10 and changes with frequency.
Electrical Specifications Table 2-3. Voltage Identification Definition (Sheet 2 of 2) VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX 0 0 1 0 0 1 0.9750 1 0 1 0 0 1 1.3500 0 0 1 0 0 0 0.9875 1 0 1 0 0 0 1.3625 0 0 0 1 1 1 1.0000 1 0 0 1 1 1 1.3750 0 0 0 1 1 0 1.0125 1 0 0 1 1 0 1.3875 0 0 0 1 0 1 1.0250 1 0 0 1 0 1 1.4000 0 0 0 1 0 0 1.0375 1 0 0 1 0 0 1.4125 0 0 0 0 1 1 1.
Electrical Specifications Note: 1. The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. System management software may utilize these signals to identify the processor installed. 2. These signals are not connected to the processor die. 3. A logic 0 is achieved by pulling the signal to ground on the package. 4. A logic 1 is achieved by leaving the signal as a no connect on the package. 2.
Electrical Specifications With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0.
Electrical Specifications Table 2-7 outlines the signals which include on-die termination (RTT). Open drain signals are also included. Table 2-8 provides signal reference voltages. Table 2-7.
Electrical Specifications connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level. 2.10 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, and have the same internal cache sizes.
Electrical Specifications Notes: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only.
Electrical Specifications Table 2-10. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes 1,13 ICC_RESET ICC_RESET for Dual-Core Intel Xeon Processor 5000 series with multiple VID (1066 MHz) 150 A 18 ICC_RESET ICC_RESET for Dual-Core Intel Xeon Processor 5063 (MV) with multiple VID 115 A 18 ITT Steady-state FSB Termination Current 6.1 A 16 ITT_POWER-UP Power-up FSB Termination Current 8.
Electrical Specifications 11. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Table 6-1. 12. This specification refers to the total reduction of the load line due to VID transitions below the specified VID. 13. Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings. 14. Baseboard bandwidth is limited to 20 MHz. 15.
Electrical Specifications Figure 2-3. Dual-Core Intel® Xeon® Processor 5000 Series (667 MHz) and Dual-Core Intel® Xeon® Processor 5063 (MV) Load Current versus Time Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-11. VCC Static and Transient Tolerance (Sheet 1 of 2) 28 ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.015 VID - 0.
Electrical Specifications Table 2-11. VCC Static and Transient Tolerance (Sheet 2 of 2) ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) 80 VID - 0.100 VID - 0.115 VID - 0.130 85 VID - 0.106 VID - 0.121 VID - 0.136 90 VID - 0.113 VID - 0.128 VID - 0.143 95 VID - 0.119 VID - 0.134 VID - 0.149 100 VID - 0.125 VID - 0.140 VID - 0.155 105 VID - 0.131 VID - 0.146 VID - 0.161 110 VID - 0.138 VID - 0.153 VID - 0.168 115 VID - 0.144 VID - 0.159 VID - 0.174 120 VID - 0.150 VID - 0.
Electrical Specifications 3. 4. Refer to Table 2-11 for processor VCC information. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and at the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for details on VR implementation.
Electrical Specifications Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Min Max Unit ILI Input Leakage Current N/A ± 200 µA ILO Output Leakage Current N/A ± 200 µA RON Buffer On Resistance 7 11 Ω Notes 1, 2 5 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open drain. 3. VHYS represents the amount of hysteresis, nominally centered about 0.
Electrical Specifications maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Table 2-17. VCC Overshoot Specifications Symbol Figure 2-5.
Mechanical Specifications 3 Mechanical Specifications The Dual-Core Intel Xeon Processor 5000 series are packaged in a Flip Chip Land Grid Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 3) Note: 34 Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
Mechanical Specifications Figure 3-3.
Mechanical Specifications Figure 3-4.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-4 for keepout zones. 3.
Mechanical Specifications 10. R is defined as the radial distance from the center of the LGA771 socket ball array to the center of heatsink load reaction point closest to the socket. 11. Applies to populated sockets in fully populated and partially populated socket configurations. 12. Through life or product. Condition must be satisfied at the beginning of life and at the end of life. 13. Rigid back is not allowed. The board should flex in the enabled configuration. 3.
Mechanical Specifications 3.8 Processor Markings Figure 3-5 and Figure 3-6 shows the topside markings on the processor. This diagram aids in the identification of the Dual-Core Intel Xeon Processor 5000 series. Figure 3-5.
Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-7 and Figure 3-8 show the top and bottom view of the processor land coordinates, respectively. The coordinates are referred to throughout the document to identify processor lands. Figure 3-7.
Mechanical Specifications Figure 3-8.
Mechanical Specifications 42 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing 4 Land Listing 4.1 Dual-Core Intel Xeon Processor 5000 Series Land Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 9) Land Name Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 2 of 9) Land Name 44 Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name Land Listing by Land Name (Sheet 3 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name 46 Land Listing by Land Name (Sheet 4 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name Land Listing by Land Name (Sheet 5 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name 48 Land Listing by Land Name (Sheet 6 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name Land Listing by Land Name (Sheet 7 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name 50 Land Listing by Land Name (Sheet 8 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing Table 4-1. Land Name Land Listing by Land Name (Sheet 9 of 9) Land Signal Buffer No. Type Direction Land Name Land Signal Buffer No.
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 9) Land No. Land Name Signal Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 2 of 9) Land Name Signal Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 3 of 9) Land No. Signal Buffer Type Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 4 of 9) Land No. Land Name Signal Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 5 of 9) Direction Land No. Land Name Signal Buffer Type C26 VTT Power/Other Source Sync Input/Output C27 VTT Power/Other D55# Source Sync Input/Output C28 VTT Power/Other VSS Power/Other C29 VTT Power/Other Land Name Signal Buffer Type B14 VSS Power/Other B15 D53# B16 B17 Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 6 of 9) Signal Buffer Type Direction Clk Input BR0# Common Clk Input/Output VTT Power/Other Land No. Land Name Signal Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 7 of 9) Signal Buffer Type Land No. Land Name Signal Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 8 of 9) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 9 of 9) Land No. Land Name Signal Buffer Type Direction Output V2 LL_ID0 Power/Other V23 VSS Power/Other Y6 A19# Source Sync Y7 VSS Power/Other Y8 VCC Power/Other Signal Buffer Type Direction A20# Source Sync Input/Output VSS Power/Other Land No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[35:3]# Type Description Notes 36 I/O A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In subphase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 2 of 8) Type Description BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Figure 7.
Signal Definitions Table 5-1. Name D[63:0]# Signal Definitions (Sheet 3 of 8) Type I/O Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. Notes 3 D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name DSTBN[3:0]# DSTBP[3:0]# Type I/O I/O Description Data strobe used to latch in D[63:0]#. Signals Associated Strobes D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 5 of 8) Type Description Notes IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 6 of 8) Type Description PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 8) Name Type Description I TESTHI[11:0] must be connected to a VTT power source through a resistor for proper processor operation. Refer to Section 2.6 for TESTHI grouping restrictions. THERMDA THERMDA2 Other Thermal Diode Anode. THERMDA connects to processor core 0, THERMDA2 connects to processor core 1. Refer to the appropriate platform design guidelines for implementation details. THERMDC THERMDC2 Other Thermal Diode Cathode.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 8 of 8) Type Description VTT P The FSB termination voltage input pins. Refer to Table 2-10 for further details. VTT_OUT O The VTT_OUT signals are included in order to provide a local VTT for some signals that require termination to VTT on the motherboard. VTTPWRGD I The processor requires this input to determine that the supply voltage for BSEL[2:0] and VID[5:0] is stable and within specification. Notes Notes: 1.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Dual-Core Intel Xeon Processor 5000 series require a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications Figure 6-2; Table 6-3 and Table 6-6) is indicative of a constrained thermal environment (that is, 1U form factor). Because of the reduced cooling capability represented by this thermal solution, the probability of TCC activation and performance loss is increased. Additionally, utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor.
Thermal Specifications Figure 6-1. Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profiles A and B TCASE_M AX is a thermal solution design point. In actuality, units will not significantly exceed TCASE_M AX_A due to TCC activation. 85 TCASE_MAX_B@ TDP 80 75 TCASE_MAX_A@ TDP Tcase [C] 70 65 Thermal Profile B Y = 0.260*x + 44.2 Thermal Profile A Y = 0.203*x + 42.6 60 55 50 45 40 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Pow e r [W] Notes: 1.
Thermal Specifications Table 6-3. Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profile B Table Power (W) Table 6-4. TCASE_MAX (° C) Power (W) TCASE_MAX (° C) P_profile_min_B=22.3 50.0 80 65.0 30 52.0 85 66.3 35 53.3 90 67.6 40 54.6 95 68.9 45 55.9 100 70.2 50 57.2 105 71.5 55 58.5 110 72.8 60 59.8 115 74.1 65 61.1 120 75.4 70 62.4 125 76.7 75 63.7 130 78.
Thermal Specifications Figure 6-2. Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Profiles TCASE_M AX is a thermal solution design point. In actuality, units w ill not significantly exceed TCASE_M AX_A due to TCC activation. 70 TCASE_MAX_B@ TDP 65 TCASE_MAX_A@ TDP Tcase [C] 60 Thermal Profile B Y = 0.260*x + 42.3 55 Thermal Profile A Y = 0.203*x + 41.7 50 45 40 0 10 20 30 40 50 60 70 80 90 100 Pow e r [W] Notes: 1.
Thermal Specifications Table 6-6. Table 6-7. Dual-Core Intel Xeon 5000 Series (667 MHz) Thermal Profile B Table Power (W) TCASE_MAX (° C) Power (W) TCASE_MAX (° C) P_profile_min_B=29.6 50.0 75 61.8 35 51.4 80 63.1 40 52.7 85 64.4 45 54.0 90 65.7 50 55.3 95 67.0 55 56.6 60 57.9 65 59.2 70 60.
Thermal Specifications Figure 6-3. Dual-Core Intel Xeon Processor 5063 (MV) Thermal Profile Thermal Profile 70 TCASE_MAX@TDP 65 Thermal Profile Y = 0.260*x + 42.3 Tcase [C] 60 55 50 45 40 0 10 20 30 40 50 60 70 80 90 100 Pow e r [W] Notes: 1. Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-8 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Dual-Core Intel® Xeon® Processor 5000 Series Thermal/Mechanical Design Guidelines. Figure 6-4. Case Temperature (TCASE) Measurement Location Note: 76 Figure is not to scale and is for reference only.
Thermal Specifications 6.2 Processor Thermal Features 6.2.1 Thermal Monitor The Thermal Monitor (TM1) feature helps control the processor temperature by activating the Thermal Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor (TM1) must be enabled for the processor to be operating within specifications.
Thermal Specifications the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the OnDemand mode. 6.2.3 PROCHOT# Signal An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has reached its factory configured trip point.
Thermal Specifications 6.2.6 Tcontrol and Fan Speed Reduction Tcontrol is a temperature specification based on a temperature reading from the thermal diode. The value for Tcontrol will be calibrated in manufacturing and configured for each processor. The Tcontrol value is set identically for both processor cores. The Tcontrol temperature for a given processor can be obtained by reading the IA32_TEMPERATURE_TARGET MSR in the processor.
Thermal Specifications between ntrim and the actual ideality of the particular processor will be calculated. This value (Tdiode_Offset) will be programmed into the new diode correction MSR and then added to the Tdiode_Base value can be used to correct temperatures read by diode based temperature sensing devices. If the ntrim value used to calculating Tdiode_Offset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate.
Thermal Specifications Table 6-10. Thermal Diode Interface Land Name Land Number Description THERMDA AL1 diode anode THERMDC AK1 diode cathode THERMDA2 AJ7 diode anode THERMDC2 AH7 diode cathode . Table 6-11. Thermal Diode Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes IFW Forward Bias Current 5 - 200 µA 1, 2 IE Emitter Current 5 - 200 µA nQ Transistor Ideality 0.997 1.001 1.005 - 3, 4, 5 Beta - 0.391 - 0.
Thermal Specifications 82 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Dual-Core Intel Xeon Processor 5000 series samples its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states. Refer to the applicable chipset specification for more information. 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Enhanced Powerdown States The Enhanced HALT power down state is enabled by default in the Dual-Core Intel Xeon Processor 5000 series.
Features The Enhanced HALT state must be enabled by way of the BIOS for the processor to remain within its specifications. The Enhanced HALT state requires support for dynamic VID transitions in the platform. Figure 7-1.
Features RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 7.2.4.1). While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state.
Features Note: Not all Dual-Core Intel Xeon Processor 5000 series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Dual-Core Intel® Xeon® Processor 5000 Series Specification Update when available. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points.
Features 88 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Dual-Core Intel® Xeon® Processor 5000 series will be offered as an Intel boxed processor.
Boxed Processor Specifications Figure 8-2. Boxed Dual-Core Intel Xeon Processor 5000 Series 2U Passive Heat Sink Figure 8-3. 2U Passive Dual-Core Intel Xeon Processor 5000 Series Thermal Solution (Exploded View) Heat sink screw springs Heat sink screws Heat sink Heat sink standoffs Thermal Interface Material Motherboard and processor Protective Tape CEK spring Chassis pan Notes: 1.
Boxed Processor Specifications 8.2.1 Boxed Processor Heat Sink Dimensions (CEK) The boxed processor will be shipped with an unattached thermal solution. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8-4 through Figure 8-8.
Boxed Processor Specifications Figure 8-4.
Boxed Processor Specifications Figure 8-5.
Boxed Processor Specifications Figure 8-6.
Boxed Processor Specifications Figure 8-7.
Boxed Processor Specifications Figure 8-8.
Boxed Processor Specifications Figure 8-9.
Boxed Processor Specifications Figure 8-10.
Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/2U active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, so a dual processor system will have up to 2100 grams total mass in the heat sinks. This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration.
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
Boxed Processor Specifications 8.3.2.1 1U Passive/2U Active Combination Heat Sink Solution (1U Rack Passive) In the 1U configuration it is assumed that a chassis duct will be implemented to provide sufficient airflow to pass through the heat sink fins. Currently the actual airflow target is within the range of 15-27 CFM. The duct should be designed as precisely as possible and should not allow any air to bypass the heat sink (0” bypass) and a back pressure of 0.38 in. H2O.
Boxed Processor Specifications The other items listed in Figure 8-3 that are required to compete this solution will be shipped with either the chassis or boards.
Debug Tools Specifications 9 Debug Tools Specifications Please refer to the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms and the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Dual-Core Intel Xeon Processor 5000 series debug port is the command and control interface for the In-Target Probe (ITP) debugger.
Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.
