Datasheet

Electrical Specifications
20 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Notes:
1. When this VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected VID range of the Dual-Core Intel Xeon Processor 5000 series [1.0750 V -
1.3500 V].
Note:
1. The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
2. These signals are not connected to the processor die.
3. A logic 0 is achieved by pulling the signal to ground on the package.
4. A logic 1 is achieved by leaving the signal as a no connect on the package.
0010010.9750
1 0 1 0 0 1 1.3500
0010000.9875
1 0 1 0 0 0 1.3625
0001111.0000
1 0 0 1 1 1 1.3750
0001101.0125
1 0 0 1 1 0 1.3875
0001011.0250
1 0 0 1 0 1 1.4000
0001001.0375
1 0 0 1 0 0 1.4125
0000111.0500
1 0 0 0 1 1 1.4250
0000101.0625
1 0 0 0 1 0 1.4375
0 0 0 0 0 1 1.0750 1 0 0 0 0 1 1.4500
0 0 0 0 0 0 1.0875 1 0 0 0 0 0 1.4625
111111OFF
1
0 1 1 1 1 1 1.4750
111110OFF
1
0 1 1 1 1 0 1.4875
1 1 1 1 0 1 1.1000 0 1 1 1 0 1 1.5000
1 1 1 1 0 0 1.1125 0 1 1 1 0 0 1.5125
1 1 1 0 1 1 1.1250 0 1 1 0 1 1 1.5250
1 1 1 0 1 0 1.1375 0 1 1 0 1 0 1.5375
1 1 1 0 0 1 1.1500 0 1 1 0 0 1 1.5500
1 1 1 0 0 0 1.1625 0 1 1 0 0 0 1.5625
1 1 0 1 1 1 1.1750 0 1 0 1 1 1 1.5750
1 1 0 1 1 0 1.1875 0 1 0 1 1 0 1.5875
1 1 0 1 0 1 1.2000 0 1 0 1 0 1 1.6000
Table 2-3. Voltage Identification Definition (Sheet 2 of 2)
VID4 VID3 VID2 VID1 VID0 VID5 V
CC_MAX
VID4 VID3 VID2 VID1 VID0 VID5 V
CC_MAX
Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1 LL_ID0 Description
00Reserved
0 1 Dual-Core Intel Xeon Processor 5000 Series
10Reserved
11Reserved
Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1 MS_ID0 Description
0 0 Dual-Core Intel Xeon Processor 5000 Series
01Reserved
10Reserved
11Reserved