Datasheet

Electrical Specifications
30 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
3. Refer to Table 2-11 for processor VCC information.
4. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and at the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for
details on VR implementation.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are based on design characterization and are not tested.
3. I
OL
is measured at 0.10*V
TT
, I
OH
is measured at 0.90*V
TT
.
4. Please refer to the appropriate platform design guide for implementation details.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
3. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
4. V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the
signal quality specifications in Section 3.
5. Leakage to V
SS
with land held at V
TT
.
6. Leakage to V
TT
with land held at 300 mV.
7. This parameter is based on design characterization and is not tested
Table 2-12. BSEL[2:0], VID[5:0] Signal Group DC Specifications
Symbol Parameter Min Max Units Notes
1
R
ON
BSEL[2:0], VID[5:0]
Buffer On Resistance
N/A 120
Ω
2
I
OL
Output Low Current N/A 2.4 mA 2, 3
I
OH
Output High Current N/A 460 µA 2, 3
V
TOL
Voltage Tolerance 0.95 * V
TT
1.05 * V
TT
V4
Table 2-13. AGTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
V
IL
Input Low Voltage 0.0 GTLREF - (0.10 * V
TT
)V 2
V
IH
Input High Voltage GTLREF + (0.10 * V
TT
)V
TT
V3, 4
V
OH
Output High Voltage 0.90 * V
TT
V
TT
V4
I
OL
Output Low Current N/A V
TT
/
(0.50 * R
TT_MIN
+ R
ON_MIN
)
mA 4
I
LI
Input Leakage Current N/A ± 200 µA 5, 6
I
LO
Output Leakage Current N/A ± 200 µA 5, 6
R
ON
Buffer On Resistance 7 11
Ω
7
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter Min Max Unit
Notes
1,
2
V
HYS
Input Hysteresis 120 396 mV 3
V
t+
PWRGOOD Input Low to
High Threshold Voltage
0.5 * (V
TT
+ V
HYS_MIN
+
0.24)
0.5 * (V
TT
+ V
HYS_MAX
+
0.24)
V
TAP Input Low to High
Threshold Voltage
0.5 * (V
TT
+ V
HYS_MIN
)0.5 * (V
TT
+ V
HYS_MAX
)V
V
t-
PWRGOOD Input High to
Low Threshold Voltage
0.4 * V
TT
0.6 * V
TT
V
TAP Input High to Low
Threshold Voltage
0.5 * (V
TT
-V
HYS_MAX
)0.5 * (V
TT
- V
HYS_MIN
)V
V
OH
Output High Voltage N/A V
TT
V4