Datasheet

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 31
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
3. V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
for all PWRGOOD and TAP
inputs.
4. PWRGOOD input and the TAP signal group must meet system signal quality specification in Section 3.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.All outputs are open drain.
3.V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4.V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the signal
quality specifications in Section 3.
6.Refer to the processor HSPICE* I/O Buffer Models for I/V characteristics.
7.The V
TT
referred to in these specifications refers to instantaneous V
TT
.
8.The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9.Leakage to V
SS
with land held at V
TT
.
10.Leakage to V
TT
with land held at 300 mV.
11.LINT0/INTR and LINT1/NMI use GTLREF_ADD as a reference voltage. For these two signals V
IH
=
GTLREF_ADD + (0.10 * V
TT
) and V
IL
= GTLREF_ADD - (0.10 * V
TT
).
2.12.1 V
CC
Overshoot Specification
The Dual-Core Intel Xeon Processor 5000 series can tolerate short transient overshoot
events where V
CC
exceeds the VID voltage when transitioning from a high-to-low
current load condition. This overshoot cannot exceed VID + V
OS_MAX
(V
OS_MAX
is the
I
LI
Input Leakage Current N/A ± 200 µA
I
LO
Output Leakage Current N/A ± 200 µA
R
ON
Buffer On Resistance 7 11
Ω
5
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Max Unit
Notes
1,
2
Table 2-15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
Symbol Parameter Min Max Unit Notes
1
V
IL
Input Low Voltage 0.0 (0.5 * V
TT
) - (0.10 * V
TT
) V 3, 11
V
IH
Input High Voltage (0.5 * V
TT
) + (0.10 * V
TT
)V
TT
V
4, 5, 7,
11
V
OH
Output High Voltage 0.90*V
TT
V
TT
V2, 5, 7
I
OL
Output Low Current -
V
TT
/
[(0.50*R
TT_MIN
)+(R
ON_MIN
)]
A8
I
LI
Input Leakage Current N/A ± 200 µA 9
I
LO
Output Leakage
Current
N/A ± 200 µA 10
R
ON
Buffer On Resistance 7 11
Ω
6
Table 2-16. VTTPWRGD DC Specifications
Symbol Parameter Min Max Unit
V
IL
Input Low Voltage 0.0 0.30 V
V
IH
Input High Voltage 0.90 V
TT
V